Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (DATE, 2020)

Enabling Reusable Physical Design Flows with Modular Flow Generators. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (CoRR, 2021)

mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (DAC, 2022)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Christopher Torng; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (ACM Trans. Reconfigurable Technol. Syst., 2023)

Onyx: A Programmable Accelerator for Sparse Tensor Algebra. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (HCS, 2024)

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (VLSI Technology and Circuits, 2024)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)

Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications. - Po-Han Chen; Bo-Wun Cheng; Michael Oduoza; Zhouhua Xie; Kalhan Koul; Sai Gautham Ravipati; Yuchen Mei; Rupert Lu; Alex Carsello; Mark Horowitz; Priyanka Raina (CICC, 2025)