A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. - Yu-Huei Lee; Shen-Yu Peng; Alex Chun-Hsien Wu; Chao-Chang Chiu; Yao-Yi Yang; Ming-Hsin Huang; Ke-Horng Chen; Ying-Hsi Lin; Shih-Wei Wang; Ching-Yuan Yeh; Chen-Chih Huang; Chao-Cheng Lee (VLSIC, 2012)

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. - Yu-Huei Lee; Shen-Yu Peng; Chao-Chang Chiu; Alex Chun-Hsien Wu; Ke-Horng Chen; Ying-Hsi Lin; Shih-Wei Wang; Tsung-Yen Tsai; Chen-Chih Huang; Chao-Cheng Lee (IEEE J. Solid State Circuits, 2013)