A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS. - George von Büren; Christian Kromer; Frank Ellinger; Alex Huber; Martin L. Schmatz; Heinz Jäckel (ISSCC, 2006)

5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS. - George von Büren; Lucio Rodoni; Heinz Jäckel; Roland Brun; Daniel Holzer; Alex Huber; Martin L. Schmatz (ESSCIRC, 2008)

Design and phase noise analysis of a multiphase 6 to 11 GHz PLL. - George von Büren; David Barras; Heinz Jäckel; Alex Huber; Christian Kromer; Marcel A. Kossel (ESSCIRC, 2009)

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS. - Lucio Rodoni; George von Büren; Alex Huber; Martin L. Schmatz; Heinz Jäckel (IEEE J. Solid State Circuits, 2009)