Software Design Issues in the Implementation of Hierarchical, Display Editors - Alex Orailoglu (1983)

Flow graph representation. - Alex Orailoglu; Daniel Gajski (DAC, 1986)

ALPS: An Algorithm for Pipeline Data Path Synthesis. - Ramesh Karri; Alex Orailoglu (MICRO, 1991)

Hierarchical Modeling of the VLSI Design Process. - Amir K. Hekmatpour; Alex Orailoglu; Paul M. Chau (IEEE Expert, 1991)

Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. - Ramesh Karri; Alex Orailoglu (DAC, 1992)

Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. - Ramesh Karri; Alex Orailoglu (FTCS, 1992)

High-Level Synthesis of Self-Recovering MicroArchitectures. - Alex Orailoglu; Ramesh Karri (ICCD, 1992)

High-Level Synthesis of Fault-Secure Microarchitectures. - Ramesh Karri; Alex Orailoglu (DAC, 1993)

Optimal Self-Recovering Microarchitecture Synthesis. - Ramesh Karri; Alex Orailoglu (FTCS, 1993)

Test Path Generation and Test Scheduling for Self-Testable Designs. - Alex Orailoglu; Ian G. Harris (ICCD, 1993)

Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. - Ian G. Harris; Alex Orailoglu (ISCAS, 1993)

Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. - Ian G. Harris; Alex Orailoglu (DAC, 1994)

Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. - Ramesh Karri; Alex Orailoglu (DAC, 1994)

Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. - Ian G. Harris; Alex Orailoglu (EDAC-ETC-EUROASIC, 1994)

Simulated annealing based yield enhancement of layouts. - Ramesh Karri; Alex Orailoglu (Great Lakes Symposium on VLSI, 1994)

SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. - Ian G. Harris; Alex Orailoglu (ICCD, 1994)

Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. - Karin Högstedt; Alex Orailoglu (ICCD, 1994)

Rapid prototyping of fault-tolerant VLSI systems. - Ramesh Karri; Karin Högstedt; Alex Orailoglu (HLSS, 1994)

Synthesis of fault-tolerant and real-time microarchitectures. - Alex Orailoglu; Ramesh Karri (J. Syst. Softw., 1994)

Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. - Alex Orailoglu; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Metric-based transformations for self testable VLSI designs with high test concurrency. - Mahsa Vahidi; Alex Orailoglu (EURO-DAC, 1995)

Towards 100% Testable FIR Digital Filters. - Laurence Goodby; Alex Orailoglu (ITC, 1995)

Testability metrics for synthesis of self-testable designs and effective test plans. - Mahsa Vahidi; Alex Orailoglu (VTS, 1995)

Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. - Laurence Goodby; Alex Orailoglu (DAC, 1996)

High-level synthesis of gracefully degradable ASICs. - Wah Chan; Alex Orailoglu (ED&TC, 1996)

Variance mismatch: identifying random-test resistance in DSP datapaths. - Laurence Goodby; Alex Orailoglu (ICASSP, 1996)

Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. - Alex Orailoglu (ICCD, 1996)

Can Defect-Tolerant Chips Better Meet the Quality Challenge? - R. L. Campbell; P. Kuekes; David Y. Lepejian; Wojciech P. Maly; Michael Nicolaidis; Alex Orailoglu (VTS, 1996)

Computer-Aided Design of Fault-Tolerant VLSI Systems. - Ramesh Karri; Karin Högstedt; Alex Orailoglu (IEEE Des. Test Comput., 1996)

Automatic Synthesis of Self-Recovering VLSI Systems. - Alex Orailoglu; Ramesh Karri (IEEE Trans. Computers, 1996)

Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors. - Ramesh Karri; Alex Orailoglu (IEEE Trans. Reliab., 1996)

Frequency-Domain Compatibility in Digital Filter BIST. - Laurence Goodby; Alex Orailoglu (DAC, 1997)

Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation. - Samuel Norman Hamilton; Alex Orailoglu (FTCS, 1997)

Microarchitectural synthesis for rapid BIST testing. - Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction. - Ian G. Harris; Alex Orailoglu (VLSI Design, 1997)

An Examination of PRPG Selection Approaches for Large, Industrial Designs. - Ismet Bayraktaroglu; K. Udawatta; Alex Orailoglu (Asian Test Symposium, 1998)

Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. - Samuel Norman Hamilton; Alex Orailoglu (DATE, 1998)

Transient and Intermittent Fault Recovery without Rollback. - Samuel Norman Hamilton; Alex Orailoglu (DFT, 1998)

Graceful Degradation in Synthesis of VLSI ICs. - Alex Orailoglu (DFT, 1998)

DFT guidance through RTL test justification and propagation analysis. - Yiorgos Makris; Alex Orailoglu (ITC, 1998)

Efficient Self-Recovering ASIC Design. - Samuel Norman Hamilton; Alex Orailoglu (IEEE Des. Test Comput., 1998)

RTL Test Justification and Propagation Analysis for Modular Designs. - Yiorgos Makris; Alex Orailoglu (J. Electron. Test., 1998)

On-Line Fault Resilience Through Gracefully Degradable ASICs. - Alex Orailoglu (J. Electron. Test., 1998)

TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation. - Yiorgos Makris; Jamison Collins; Alex Orailoglu; Praveen Vishakantaiah (CICC, 1999)

Self Recovering Controller and Datapath Codesign. - Samuel Norman Hamilton; Alex Orailoglu; Andre Hertwig (DATE, 1999)

Channel-Based Behavioral Test Synthesis for Improved Module Reachability. - Yiorgos Makris; Alex Orailoglu (DATE, 1999)

A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. - Yiorgos Makris; Alex Orailoglu (DFT, 1999)

Low-Cost Test for Large Analog IC's. - Sule Ozev; Alex Orailoglu (DFT, 1999)

Property-based testability analysis for hierarchical RTL designs. - Yiorgos Makris; Alex Orailoglu (ICECS, 1999)

Low-Cost On-Line Test for Digital Filters. - Ismet Bayraktaroglu; Alex Orailoglu (VTS, 1999)

Redundancy and testability in digital filter datapaths. - Laurence Goodby; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Accumulation-based concurrent fault detection for linear digital state variable systems. - Ismet Bayraktaroglu; Alex Orailoglu (Asian Test Symposium, 2000)

Fast hierarchical test path construction for DFT-free controller-datapath circuits. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (Asian Test Symposium, 2000)

Modular test generation and concurrent transparency-based test translation using gate-level ATPG. - Yiorgos Makris; Alex Orailoglu; Praveen Vishakantaiah (CICC, 2000)

Improved fault diagnosis in scan-based BIST via superposition. - Ismet Bayraktaroglu; Alex Orailoglu (DAC, 2000)

Test Quality and Fault Risk in Digital Filter Datapath BIST. - Laurence Goodby; Alex Orailoglu (DATE, 2000)

Test Synthesis for Mixed-Signal SOC Paths. - Sule Ozev; Ismet Bayraktaroglu; Alex Orailoglu (DATE, 2000)

Low cost concurrent test implementation for linear digital systems. - Ismet Bayraktaroglu; Alex Orailoglu (ETW, 2000)

How to avoid random walks in hierarchical test path identification. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (ETW, 2000)

Cost effective digital filter design for concurrent test. - Ismet Bayraktaroglu; Alex Orailoglu (ICASSP, 2000)

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters. - Ismet Bayraktaroglu; Alex Orailoglu (ISCAS, 2000)

Transparency-based hierarchical test generation for modular RTL designs. - Yiorgos Makris; Jamison Collins; Alex Orailoglu; Praveen Vishakantaiah (ISCAS, 2000)

Deterministic partitioning techniques for fault diagnosis in scan-based BIST. - Ismet Bayraktaroglu; Alex Orailoglu (ITC, 2000)

Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test. - Yiorgos Makris; Alex Orailoglu (LATW, 2000)

Block-Based Test Integration for Analog Integrated Circuits. - Sule Ozev; Alex Orailoglu (LATW, 2000)

Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. - Yiorgos Makris; Ismet Bayraktaroglu; Alex Orailoglu (VTS, 2000)

Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. - Sule Ozev; Alex Orailoglu (VTS, 2000)

On-line test for fault-secure fault identification. - Samuel Norman Hamilton; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. - Sobeeh Almukhaizim; Peter Petrov; Alex Orailoglu (Asian Test Symposium, 2001)

Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? - Ismet Bayraktaroglu; Alex Orailoglu (Asian Test Symposium, 2001)

Compaction Schemes with Minimum Test Application Time. - Ozgur Sinanoglu; Alex Orailoglu (Asian Test Symposium, 2001)

Low-cost, software-based self-test methodologies for performance faults in processor control subsystems. - Sobeeh Almukhaizim; Peter Petrov; Alex Orailoglu (CICC, 2001)

Towards effective embedded processors in codesigns: customizable partitioned caches. - Peter Petrov; Alex Orailoglu (CODES, 2001)

Test Volume and Application Time Reduction Through Scan Chain Concealment. - Ismet Bayraktaroglu; Alex Orailoglu (DAC, 2001)

Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. - Peter Petrov; Alex Orailoglu (DAC, 2001)

Diagnosis for scan-based BIST: reaching deep into the signatures. - Ismet Bayraktaroglu; Alex Orailoglu (DATE, 2001)

Data cache energy minimizations through programmable tag size matching to the applications. - Peter Petrov; Alex Orailoglu (ISSS, 2001)

Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. - Christian Olgaard; Sule Ozev; Alex Orailoglu (ITC, 2001)

Space and time compaction schemes for embedded cores. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2001)

Improved Methods for Fault Diagnosis in Scan-Based BIST. - Ismet Bayraktaroglu; Alex Orailoglu (LATW, 2001)

Efficient Transparency Extraction and Utilization in Hierarchical Test. - Yiorgos Makris; Vishal Patel; Alex Orailoglu (VTS, 2001)

RT-level Fault Simulation Based on Symbolic Propagation. - Ozgur Sinanoglu; Alex Orailoglu (VTS, 2001)

Concurrent test for digital linear systems. - Ismet Bayraktaroglu; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Performance and power effectiveness in embedded processors customizable partitioned caches. - Peter Petrov; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. - Yiorgos Makris; Alex Orailoglu (Asian Test Symposium, 2002)

Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. - Peter Petrov; Alex Orailoglu (CODES, 2002)

Gate Level Fault Diagnosis in Scan-Based BIST. - Ismet Bayraktaroglu; Alex Orailoglu (DATE, 2002)

Test Planning and Design Space Exploration in a Core-Based Environment. - Érika F. Cota; Luigi Carro; Marcelo Lubaszewski; Alex Orailoglu (DATE, 2002)

Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. - Peter Petrov; Alex Orailoglu (DATE, 2002)

Reducing Test Application Time Through Test Data Mutation Encoding. - Sherief Reda; Alex Orailoglu (DATE, 2002)

Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. - Ozgur Sinanoglu; Alex Orailoglu (DFT, 2002)

Dynamic test data transformations for average and peak power reductions. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (ETW, 2002)

A novel scan architecture for power-efficient, rapid test. - Ozgur Sinanoglu; Alex Orailoglu (ICCAD, 2002)

Fault Dictionary Size Reduction through Test Response Superposition. - Baris Arslan; Alex Orailoglu (ICCD, 2002)

Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. - Sule Ozev; Alex Orailoglu (ICCD, 2002)

Automated test development and test time reduction for RF subsystems. - Sule Ozev; Alex Orailoglu; Hosam Haggag (ISCAS (1), 2002)

An Integrated Tool for Analog Test Generation and Fault Simulation. - Sule Ozev; Alex Orailoglu (ISQED, 2002)

On the Relation between SAT and BDDs for Equivalence Checking. - Sherief Reda; Rolf Drechsler; Alex Orailoglu (ISQED, 2002)

Low-Power Data Memory Communication for Application-Specific Embedded Processors. - Alex Orailoglu; Peter Petrov (ISSS, 2002)

Scan Power Reduction Through Test Data Transition Frequency Analysis. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (ITC, 2002)

Generic and Detailed Search for TAM Definition in Core-Based Systems. - Érika F. Cota; Luigi Carro; Alex Orailoglu; Marcelo Lubaszewski (LATW, 2002)

Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. - Sule Ozev; Alex Orailoglu (VTS, 2002)

Test Power Reduction through Minimization of Scan Chain Transitions. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (VTS, 2002)

Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. - Ismet Bayraktaroglu; Alex Orailoglu (IEEE Des. Test Comput., 2002)

Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. - Sule Ozev; Christian Olgaard; Alex Orailoglu (IEEE Des. Test Comput., 2002)

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (J. Electron. Test., 2002)

Efficient Construction of Aliasing-Free Compaction Circuitry. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Micro, 2002)

Microarchitectural synthesis of performance-constrained, low-power VLSI designs. - Laurence Goodby; Alex Orailoglu; Paul M. Chau (ACM Trans. Design Autom. Electr. Syst., 2002)

Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. - Baris Arslan; Alex Orailoglu (Asian Test Symposium, 2003)

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. - Ozgur Sinanoglu; Alex Orailoglu (Asian Test Symposium, 2003)

Test application time and volume compression through seed overlapping. - Wenjing Rao; Ismet Bayraktaroglu; Alex Orailoglu (DAC, 2003)

Power Efficiency through Application-Specific Instruction Memory Transformations. - Peter Petrov; Alex Orailoglu (DATE, 2003)

Virtual Compression through Test Vector Stitching for Scan Based Designs. - Wenjing Rao; Alex Orailoglu (DATE, 2003)

Customizable Embedded Processor Architectures. - Peter Petrov; Alex Orailoglu (DSD, 2003)

Low-power Branch Target Buffer for Application-Specific Embedded Processors. - Peter Petrov; Alex Orailoglu (DSD, 2003)

Hierarchical Constraint Conscious RT-level Test Generation. - Ozgur Sinanoglu; Alex Orailoglu (DSD, 2003)

Parity-based output compaction for core-based SOCs [logic testing]. - Ozgur Sinanoglu; Alex Orailoglu (ETW, 2003)

Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. - Peter Petrov; Alex Orailoglu (ICCAD, 2003)

Partial Core Encryption for Performance-Efficient Test of SOCs. - Ozgur Sinanoglu; Alex Orailoglu (ICCAD, 2003)

Virtual Page Tag Reduction for Low-power TLBs. - Peter Petrov; Alex Orailoglu (ICCD, 2003)

Aggressive Test Power Reduction Through Test Stimuli Transformation. - Ozgur Sinanoglu; Alex Orailoglu (ICCD, 2003)

Modeling Scan Chain Modifications For Scan-in Test Power Minimization. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2003)

Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. - Ismet Bayraktaroglu; Alex Orailoglu (VTS, 2003)

Guest Editors' Introduction: Application-Specific Microprocessors. - Alex Orailoglu; Alexander V. Veidenbaum (IEEE Des. Test Comput., 2003)

Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. - Peter Petrov; Alex Orailoglu (IEEE Des. Test Comput., 2003)

Compacting Test Responses for Deeply Embedded SoC Cores. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Des. Test Comput., 2003)

Statistical Tolerance Analysis for Assured Analog Test Coverage. - Sule Ozev; Alex Orailoglu (J. Electron. Test., 2003)

Reducing Average and Peak Test Power Through Scan Chain Modification. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (J. Electron. Test., 2003)

Guest Editor's Introduction. - Alex Orailoglu (Int. J. Parallel Program., 2003)

Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. - Ismet Bayraktaroglu; Alex Orailoglu (IEEE Trans. Computers, 2003)

Efficient RT-level fault diagnosis methodology. - Ozgur Sinanoglu; Alex Orailoglu (ASP-DAC, 2004)

On mismatch in the deep sub-micron era - from physics to circuits. - Rasit Onur Topaloglu; Alex Orailoglu (ASP-DAC, 2004)

CircularScan: A Scan Architecture for Test Cost Reduction. - Baris Arslan; Alex Orailoglu (DATE, 2004)

Scan Power Minimization through Stimulus and Response Transformations. - Ozgur Sinanoglu; Alex Orailoglu (DATE, 2004)

Pipelined test of SOC cores through test data transformations. - Ozgur Sinanoglu; Alex Orailoglu (ETS, 2004)

Design space exploration for aggressive test cost reduction in CircularScan architectures. - Baris Arslan; Alex Orailoglu (ICCAD, 2004)

Frugal linear network-based test decompression for drastic test cost reductions. - Wenjing Rao; Alex Orailoglu; George Su (ICCAD, 2004)

Extending the Applicability of Parallel-Serial Scan Designs. - Baris Arslan; Ozgur Sinanoglu; Alex Orailoglu (ICCD, 2004)

End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. - Sule Ozev; Alex Orailoglu (ICCD, 2004)

Test Cost Reduction Through A Reconfigurable Scan Architecture. - Baris Arslan; Alex Orailoglu (ITC, 2004)

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ITC, 2004)

Autonomous Yet Deterministic Test of SOC Cores. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2004)

Application specific instruction memory transformations for power efficient, fault resilient embedded processors. - Raid Ayoub; Peter Petrov; Alex Orailoglu (SoCC, 2004)

Seamless Test of Digital Components in Mixed-Signal Paths. - Sule Ozev; Ismet Bayraktaroglu; Alex Orailoglu (IEEE Des. Test Comput., 2004)

Searching for Global Test Costs Optimization in Core-Based Systems. - Érika F. Cota; Luigi Carro; Marcelo Lubaszewski; Alex Orailoglu (J. Electron. Test., 2004)

Fast and energy-frugal deterministic test through efficient compression and compaction techniques. - Ozgur Sinanoglu; Alex Orailoglu (J. Syst. Archit., 2004)

Transforming Binary Code for Low-Power Embedded Processors. - Peter Petrov; Alex Orailoglu (IEEE Micro, 2004)

Tag compression for low power in dynamically customizable embedded processors. - Peter Petrov; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. - Yiorgos Makris; Ismet Bayraktaroglu; Alex Orailoglu (IEEE Trans. Reliab., 2004)

Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. - Sule Ozev; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Low-power instruction bus encoding for embedded processors. - Peter Petrov; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. - Raid Ayoub; Alex Orailoglu (ASP-DAC, 2005)

Fault tolerant nanoelectronic processor architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ASP-DAC, 2005)

Forward discrete probability propagation method for device performance characterization under process variations. - Rasit Onur Topaloglu; Alex Orailoglu (ASP-DAC, 2005)

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. - Tongquan Wei; Kaijie Wu 001; Ramesh Karri; Alex Orailoglu (ASP-DAC, 2005)

Energy-effcient physically tagged caches for embedded processors with virtual memory. - Peter Petrov; Daniel Tracy; Alex Orailoglu (DAC, 2005)

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. - Rasit Onur Topaloglu; Alex Orailoglu (DAC, 2005)

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ICCD, 2005)

Efficient RT-Level Fault Diagnosis. - Ozgur Sinanoglu; Alex Orailoglu (J. Comput. Sci. Technol., 2005)

The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. - Ismet Bayraktaroglu; Alex Orailoglu (IEEE Trans. Computers, 2005)

A reprogrammable customization framework for efficient branch resolution in embedded processors. - Peter Petrov; Alex Orailoglu (ACM Trans. Embed. Comput. Syst., 2005)

Test power reductions through computationally efficient, decoupled scan chain modifications. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Trans. Reliab., 2005)

Power-efficient instruction delivery through trace reuse. - Chengmo Yang; Alex Orailoglu (PACT, 2006)

Power efficient branch prediction through early identification of branch addresses. - Chengmo Yang; Alex Orailoglu (CASES, 2006)

Topology aware mapping of logic functions onto nanowire-based crossbar architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DAC, 2006)

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (ETS, 2006)

Power-Constrained SOC Test Schedules through Utilization of Functional Buses. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (ICCD, 2006)

Decision Tree Based Mismatch Diagnosis in Analog Circuits. - Mingjing Chen; Hosam Haggag; Alex Orailoglu (VTS, 2006)

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (VTS, 2006)

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (ASP-DAC, 2007)

Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements. - Mingjing Chen; Alex Orailoglu (ATS, 2007)

Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. - Chengmo Yang; Alex Orailoglu (CASES, 2007)

Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. - Chengmo Yang; Alex Orailoglu (CODES+ISSS, 2007)

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DATE, 2007)

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (DSN, 2007)

Power efficient register file update approach for embedded processors. - Raid Ayoub; Alex Orailoglu (ICCD, 2007)

Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. - Mingjing Chen; Alex Orailoglu (ICCD, 2007)

Design automation for hybrid CMOS-nonoelectronics crossbars. - Kyosun Kim; Ramesh Karri; Alex Orailoglu (NANOARCH, 2007)

Architectures for Silicon Nanoelectronics and Beyond. - R. Iris Bahar; Dan W. Hammerstrom; Justin E. Harlow III; William H. Joyner Jr.; Clifford Lau; Diana Marculescu; Alex Orailoglu; Massoud Pedram (Computer, 2007)

Towards Nanoelectronics Processor Architectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (J. Electron. Test., 2007)

Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. - Peter Petrov; Alex Orailoglu (Int. J. Parallel Program., 2007)

On the identification of modular test requirements for low cost hierarchical test path construction. - Yiorgos Makris; Alex Orailoglu (Integr., 2007)

Guest Editorial. - Clifford Lau; Alex Orailoglu; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization. - Chengmo Yang; Alex Orailoglu (CASES, 2008)

Application specific non-volatile primary memory for embedded systems. - Kwangyoon Lee; Alex Orailoglu (CODES+ISSS, 2008)

Miss reduction in embedded processors through dynamic, power-friendly cache design. - Garo Bournoutian; Alex Orailoglu (DAC, 2008)

Towards fault tolerant parallel prefix adders in nanoelectronic systems. - Wenjing Rao; Alex Orailoglu (DATE, 2008)

Test cost minimization through adaptive test development. - Mingjing Chen; Alex Orailoglu (ICCD, 2008)

Online test and fault-tolerance for nanoelectronic programmable logic arrays. - Saturnino Garcia; Alex Orailoglu (NANOARCH, 2008)

Locality aware redundancy allocation in nanoelectronic systems. - Wenjing Rao; Alex Orailoglu; Keith Marzullo (NANOARCH, 2008)

Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. - Kwangyoon Lee; Alex Orailoglu (SASP, 2008)

Scheduling Power-Constrained Tests through the SoC Functional Bus. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Filtering Global History: Power and Performance Efficient Branch Predictor. - Raid Ayoub; Alex Orailoglu (ASAP, 2009)

Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. - Chengmo Yang; Mingjing Chen; Alex Orailoglu (CODES+ISSS, 2009)

Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy. - Saturnino Garcia; Alex Orailoglu (DATE, 2009)

Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. - Chengmo Yang; Alex Orailoglu (DATE, 2009)

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience. - Mingjing Chen; Alex Orailoglu (DFT, 2009)

Processor reliability enhancement through compiler-directed register file peak temperature reduction. - Chengmo Yang; Alex Orailoglu (DSN, 2009)

Deflecting crosstalk by routing reconsideration through refined signal correlation estimation. - Mingjing Chen; Alex Orailoglu (ACM Great Lakes Symposium on VLSI, 2009)

Scan power reduction in linear test data compression scheme. - Mingjing Chen; Alex Orailoglu (ICCAD, 2009)

Logic Mapping in Crossbar-Based Nanoarchitectures. - Wenjing Rao; Alex Orailoglu; Ramesh Karri (IEEE Des. Test Comput., 2009)

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks. - Ozgur Sinanoglu; Mohammed Al-Mulla; Noora A. Shunaiber; Alex Orailoglu (J. Comput. Sci. Technol., 2009)

Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008. - Alex Orailoglu; Laura Pozzi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture. - Dong Xiang; Dianwei Hu; Qiang Xu 001; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Dynamic, non-linear cache architecture for power-sensitive mobile processors. - Garo Bournoutian; Alex Orailoglu (CODES+ISSS, 2010)

High durability in NAND flash memory through effective page reuse mechanisms. - Kwangyoon Lee; Alex Orailoglu (CODES+ISSS, 2010)

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. - Mingjing Chen; Alex Orailoglu (DATE, 2010)

Performance and energy efficient cache migrationapproach for thermal management in embedded systems. - Raid Ayoub; Alex Orailoglu (ACM Great Lakes Symposium on VLSI, 2010)

Delay test quality maximization through process-aware selection of test set size. - Baris Arslan; Alex Orailoglu (ICCD, 2010)

Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations. - Chengmo Yang; Alex Orailoglu (VLSI-SoC, 2010)

Fine-grained adaptive CMP cache sharing through access history exploitation. - Chengmo Yang; Chun Jason Xue; Alex Orailoglu (VLSI-SoC, 2010)

VDDmin test optimization for overscreening minimization through adaptive scan chain masking. - Mingjing Chen; Alex Orailoglu (VTS, 2010)

Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. - Garo Bournoutian; Alex Orailoglu (Des. Autom. Embed. Syst., 2010)

Squashing code size in microcoded IPs while delivering high decompression speed. - Chengmo Yang; Mingjing Chen; Alex Orailoglu (Des. Autom. Embed. Syst., 2010)

DiSC: A New Diagnosis Method for Multiple Scan Chain Failures. - Sunghoon Chun; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost. - Baris Arslan; Alex Orailoglu (Asian Test Symposium, 2011)

Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors. - Garo Bournoutian; Alex Orailoglu (CODES+ISSS, 2011)

Diagnosing scan clock delay faults through statistical timing pruning. - Mingjing Chen; Alex Orailoglu (DAC, 2011)

Adaptive test optimization through real time learning of test effectiveness. - Baris Arslan; Alex Orailoglu (DATE, 2011)

Diagnosing scan chain timing faults through statistical feature analysis of scan images. - Mingjing Chen; Alex Orailoglu (DATE, 2011)

Register allocation for simultaneous reduction of energy and peak temperature on registers. - Tiantian Liu 001; Alex Orailoglu; Chun Jason Xue; Minming Li (DATE, 2011)

Frugal but flexible multicore topologies in support of resource variation-driven adaptivity. - Chengmo Yang; Alex Orailoglu (DATE, 2011)

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge. - Wenjing Rao; Chengmo Yang; Ramesh Karri; Alex Orailoglu (Computer, 2011)

Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability. - Yuping Zhang; Chun Jason Xue; Chengmo Yang; Alex Orailoglu (J. Parallel Distributed Comput., 2011)

Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface. - Chengmo Yang; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Dynamic transient fault detection and recovery for embedded processor datapaths. - Garo Bournoutian; Alex Orailoglu (CODES+ISSS, 2012)

Delay test resource allocation and scheduling for multiple frequency domains. - Baris Arslan; Alex Orailoglu (VTS, 2012)

Small-delay defects detection under process variation using Inter-Path Correlation. - Francisco J. Galarza-Medina; Jose Luis Garcia-Gervacio; Víctor H. Champac; Alex Orailoglu (VTS, 2012)

On Diagnosis of Timing Failures in Scan Architecture. - Mingjing Chen; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Tackling Resource Variations Through Adaptive Multicore Execution Frameworks. - Chengmo Yang; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection. - Mingjing Chen; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Full exploitation of process variation space for continuous delivery of optimal delay test quality. - Baris Arslan; Alex Orailoglu (ASP-DAC, 2013)

Profit maximization through process variation aware high level synthesis with speed binning. - Mengying Zhao; Alex Orailoglu; Chun Jason Xue (DATE, 2013)

Tracing the best test mix through multi-variate quality tracking. - Baris Arslan; Alex Orailoglu (VTS, 2013)

Towards a cost-effective hardware trojan detection methodology. - Raymond Paseman; Alex Orailoglu (VTS, 2013)

Application-aware adaptive cache architecture for power-sensitive mobile processors. - Garo Bournoutian; Alex Orailoglu (ACM Trans. Embed. Comput. Syst., 2013)

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers. - Tiantian Liu 001; Alex Orailoglu; Chun Jason Xue; Minming Li (ACM Trans. Embed. Comput. Syst., 2013)

On-device objective-C application optimization framework for high-performance mobile processors. - Garo Bournoutian; Alex Orailoglu (DATE, 2014)

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory. - Chenchen Fu; Mengying Zhao; Chun Jason Xue; Alex Orailoglu (ISLPED, 2014)

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems. - Keni Qiu; Mengying Zhao; Chun Jason Xue; Alex Orailoglu (ACM Trans. Embed. Comput. Syst., 2014)

Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test. - Mingjing Chen; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power. - Garo Bournoutian; Alex Orailoglu (ARCS, 2015)

Mobile ecosystem driven application-specific low-power control microarchitecture. - Garo Bournoutian; Alex Orailoglu (ICCD, 2015)

Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning. - Mengying Zhao; Alex Orailoglu; Chun Jason Xue (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains. - Baris Arslan; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment. - Baris Arslan; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Ensuring system security through proximity based authentication. - Joshua Marxen; Alex Orailoglu (ASP-DAC, 2017)

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. - Fakir Sharif Hossain; Tomokazu Yoneda; Michihiro Shintani; Michiko Inoue; Alex Orailoglu (ATS, 2017)

Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. - Fakir Sharif Hossain; Tomokazu Yoneda; Michiko Inoue; Alex Orailoglu (ETS, 2017)

Variation-Aware Hardware Trojan Detection through Power Side-channel. - Fakir Sharif Hossain; Michihiro Shintani; Michiko Inoue; Alex Orailoglu (ITC, 2018)

The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures. - Elbruz Ozen; Alex Orailoglu (ARCS, 2019)

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications. - Elbruz Ozen; Alex Orailoglu (ATS, 2019)

Piercing Logic Locking Keys through Redundancy Identification. - Leon Li; Alex Orailoglu (DATE, 2019)

Detecting Gas Vapor Leaks through Uncalibrated Sensor Based CPS. - Diaa Badawi; Sule Ozev; Jennifer Blain Christen; Chengmo Yang; Alex Orailoglu; A. Enis Çetin (ICASSP, 2019)

Shielding Logic Locking from Redundancy Attacks. - Leon Li; Alex Orailoglu (VTS, 2019)

Detecting Gas Vapor Leaks Using Uncalibrated Sensors. - Diaa Badawi; Tuba Ayhan; Sule Ozev; Chengmo Yang; Alex Orailoglu; Ahmet Enis Çetin (IEEE Access, 2019)

Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions. - Elbruz Ozen; Alex Orailoglu (ASP-DAC, 2020)

Hunting Sybils in Participatory Mobile Consensus-Based Networks. - Nickolai Verchok; Alex Orailoglu (AsiaCCS, 2020)

Test Pattern Superposition to Detect Hardware Trojans. - Chris Nigh; Alex Orailoglu (DATE, 2020)

Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression. - Elbruz Ozen; Alex Orailoglu (ICCAD, 2020)

A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration. - Chengmo Yang; Patrick Cronin; Agamyrat Agambayev; Sule Ozev; A. Enis Çetin; Alex Orailoglu (ICCAD, 2020)

Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks. - Elbruz Ozen; Alex Orailoglu (ECML/PKDD (2), 2020)

Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns. - Chris Nigh; Alex Orailoglu (VTS, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums. - Elbruz Ozen; Alex Orailoglu (J. Electron. Test., 2020)

Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection. - Elbruz Ozen; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis. - Leon Li; Shuyi Ni; Alex Orailoglu (HOST, 2021)

Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs. - Elbruz Ozen; Alex Orailoglu (ICCAD, 2021)

SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks. - Elbruz Ozen; Alex Orailoglu (ACM Trans. Embed. Comput. Syst., 2021)

AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction. - Chris Nigh; Alex Orailoglu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption. - Leon Li; Alex Orailoglu (DATE, 2022)

Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020). - Marc Reichenbach; Matthias Jung 001; Alex Orailoglu (Int. J. Parallel Program., 2022)

Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation. - Elbruz Ozen; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box. - Leon Li; Alex Orailoglu (ATS, 2023)

Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation. - Leon Li; Alex Orailoglu (VTS, 2023)

Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation. - Elbruz Ozen; Alex Orailoglu (IEEE Des. Test, 2023)

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis. - Leon Li; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design. - Elbruz Ozen; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Transcoders: A Better Alternative To Denoising Autoencoders. - Pushpak Raj Gautam; Alex Orailoglu (ETS, 2024)

Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation. - Leon Li; Alex Orailoglu (ITC, 2024)

Special Issue on SAMOS 2022. - Alex Orailoglu; Marc Reichenbach; Matthias Jung 001 (Int. J. Parallel Program., 2024)

White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse Engineering. - Leon Li; Alex Orailoglu (ASP-DAC, 2025)

Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering. - Leon Li; Alex Orailoglu (ISVLSI, 2025)

Linear Algorithmic Checksums for Deep-Neural-Network Error Detection: Fundamentals and Recent Advancements. - Elbruz Ozen; Ozgur Ozerdem; Alex Orailoglu (IEEE Des. Test, 2025)