An x86-64 core implemented in 32nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Greg Constant; Amy Novak; Sam Naffziger (ISSCC, 2010)

An x86-64 Core in 32 nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Amy Novak; Sam Naffziger (IEEE J. Solid State Circuits, 2011)

3.2 Zen: A next-generation high-performance ×86 core. - Teja Singh; Sundar Rangarajan; Deepesh John; Carson Henrion; Shane Southard; Hugh McIntyre; Amy Novak; Stephen Kosonocky; Ravi Jotwani; Alex Schaefer; Edward Chang; Joshua Bell; et al. (ISSCC, 2017)

Zen: An Energy-Efficient High-Performance × 86 Core. - Teja Singh; Alex Schaefer; Sundar Rangarajan; Deepesh John; Carson Henrion; Russell Schreiber; Miguel Rodriguez; Stephen Kosonocky; Samuel Naffziger; Amy Novak (IEEE J. Solid State Circuits, 2018)

The dimension of the negative cycle vectors of a signed graph. - Alex Schaefer; Thomas Zaslavsky (Ars Math. Contemp., 2019)

2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core. - Teja Singh; Sundar Rangarajan; Deepesh John; Russell Schreiber; Spence Oliver; Rajit Seahra; Alex Schaefer (ISSCC, 2020)

Strongly connectable digraphs and non-transitive dice. - Simon Joyce; Alex Schaefer; Douglas B. West; Thomas Zaslavsky (AKCE Int. J. Graphs Comb., 2020)

Graphs that contain multiply transitive matchings. - Alex Schaefer; Eric Swartz (Eur. J. Comb., 2021)

"Zen 5": The AMD High-Performance 4nm x86-64 Microprocessor Core. - Teja Singh; Spence Oliver; Sundar Rangarajan; Shane Southard; Carson Henrion; Alex Schaefer; Brett Johnson; Sarah Bartaszewicz Tower; Kathy Hoover; Deepesh John; Ted Antoniadis; Shravan Lakshman; et al. (ISSCC, 2025)