Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. - Michael V. Goncharov; Alexander B. Smirnov; Nikolai Starodoubtsev; Ilya V. Klotchkov (ACSD, 1998)

Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs. - Nikolai Starodoubtsev; Sergei Bystrov; Michael V. Goncharov; Ilya V. Klotchkov; Alexander B. Smirnov (ACSD, 2001)

A Case Study for the Verification of Complex Timed Circuits: IPCMOS. - Marco A. Peña; Jordi Cortadella; Alexander B. Smirnov; Enric Pastor (DATE, 2002)

An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. - Alexander B. Smirnov; Alexander Taubin; Ming Su; Mark G. Karpovsky (ACSD, 2005)

Delay Insensitive Encoding and Power Analysis: A Balancing Act. - Konrad J. Kulikowski; Ming Su; Alexander B. Smirnov; Alexander Taubin; Mark G. Karpovsky; Daniel MacDonald (ASYNC, 2005)

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. - Konrad J. Kulikowski; Alexander B. Smirnov; Alexander Taubin (CHES, 2006)

Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines. - Alexander B. Smirnov; Alexander Taubin (ASYNC, 2009)