Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. - Sung-Mo Kang; Robert H. Krambeck; Hung-Fai Stephen Law; Alexander D. Lopez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology. - Ramautar Sharma; Alexander D. Lopez; John A. Michejda; Steven J. Hillenius; John M. Andrews; Arnold J. Studwell (IEEE J. Solid State Circuits, 1989)