An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS. - Alexander Edward; Pak Kwong Chan (IEICE Trans. Electron., 2012)

General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. - Alexander Edward; José Silva-Martínez (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (VLSIC, 2015)

A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. - Carlos Briseno-Vidrios; Alexander Edward; Negar Rashidi; José Silva-Martínez (IEEE J. Solid State Circuits, 2016)

A 13bit 200MS/S pipeline ADC with current-mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; José Silva-Martínez (ISCAS, 2017)

High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. - Qiyuan Liu 001; Alexander Edward; Carlos Briseno-Vidrios; Negar Rashidi; José Silva-Martínez (MWSCAS, 2017)

A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. - Carlos Briseno-Vidrios; Alexander Edward; Ayman Shafik; Samuel Palermo; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. - Alexander Edward; Qiyuan Liu 001; Carlos Briseno-Vidrios; Martin Kinyua; Eric G. Soenen; Aydin Ilker Karsilayan; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. - Qiyuan Liu 001; Alexander Edward; Martin Kinyua; Eric G. Soenen; José Silva-Martínez (IEEE J. Solid State Circuits, 2017)

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2018)

A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. - Qiyuan Liu 001; Alexander Edward; Dadian Zhou; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2018)