Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. - Alexander Hepp; Georg Sigl (CF, 2021)

Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. - Alexander Hepp; Johanna Baehr 001; Georg Sigl (DATE, 2022)

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. - Bernhard Lippmann; Ann-Christin Bette; Matthias Ludwig 005; Johannes Mutter; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser; Nicola Kovac; Tobias Zweifel; Martin Rasche; Oliver Kellermann (DATE, 2022)

Hardware Obfuscation of Digital FIR Filters. - Levent Aksoy; Alexander Hepp; Johanna Baehr 001; Samuel Pagliarini (DDECS, 2022)

Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. - Johanna Baehr 001; Alexander Hepp; Michaela Brunner; Maja Malenko; Georg Sigl (DSD, 2022)

A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. - Alexander Hepp; Tiago D. Perez; Samuel Pagliarini; Georg Sigl (ICCAD, 2022)

Toward a Human-Readable State Machine Extraction. - Michaela Brunner; Alexander Hepp; Johanna Baehr 001; Georg Sigl (ACM Trans. Design Autom. Electr. Syst., 2022)

Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. - Michaela Brunner; Hye-Hyun Lee; Alexander Hepp; Johanna Baehr 001; Georg Sigl (DDECS, 2024)

Trojan Assets and Attack Vectors in Processors. - Czea Sie Chuah; Alexander Hepp; Christian Appold; Tim Leinmüller (ISQED, 2024)

RISC-V Triplet: Tapeouts for Security Applications. - Jonas Schupp; Patrick Karl; Jens Nöpel; Alexander Hepp; Tim Music; Georg Sigl (NorCAS, 2024)

Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC). - Bernhard Lippmann; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser (DATE, 2025)