PLA optimization using output encoding. - Alexander Saldanha; Randy H. Katz (ICCAD, 1988)

Multi-level Logic Simplification Using Don't Cares and Filters. - Alexander Saldanha; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1989)

Timing Optimization with Testability Considerations. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli; Kwang-Ting Cheng (ICCAD, 1990)

A Framework for Satisfying Input and Output Encoding Constraints. - Alexander Saldanha; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1991)

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. - Patrick C. McGeer; Alexander Saldanha; Paul R. Stephan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Is redundancy necessary to reduce delay? - Kurt Keutzer; Sharad Malik; Alexander Saldanha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Delay Fault Coverage and Performance Tradeoffs. - William K. C. Lam; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

Performance Optimization Using Exact Sensitization. - Alexander Saldanha; Heather Harkness; Patrick C. McGeer; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Circuit structure relations to redundancy and delay. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Satisfaction of input and output encoding constraints. - Alexander Saldanha; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Supervisory Control of Finite State Machines. - Adnan Aziz; Felice Balarin; Robert K. Brayton; Marika Domenica Di Benedetto; Alexander Saldanha (CAV, 1995)

Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. - Luciano Lavagno; Patrick C. McGeer; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli (DAC, 1995)

Fast discrete function evaluation using decision diagrams. - Patrick C. McGeer; Kenneth L. McMillan; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli; Patrick Scaglia (ICCAD, 1995)

Functional clock schedule optimization. - Alexander Saldanha; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1995)

Delay fault coverage, test set size, and performance trade-offs. - William K. C. Lam; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Verification of Electronic Systems. - Alberto L. Sangiovanni-Vincentelli; Patrick C. McGeer; Alexander Saldanha (DAC, 1996)

Compact and complete test set generation for multiple stuck-faults. - Alok Agrawal; Alexander Saldanha; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1996)

Trace driven logic synthesis - application to power minimization. - Luca P. Carloni; Patrick C. McGeer; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Approximate timing analysis of combinational circuits under the XBD0 model. - Yuji Kukimoto; Wilsin Gosti; Alexander Saldanha; Robert K. Brayton (ICCAD, 1997)

Symbolic two-level minimization. - Tiziano Villa; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

An Exact Input Encoding Algorithm for BDDs Representing FSMs. - Wilsin Gosti; Alberto L. Sangiovanni-Vincentelli; Tiziano Villa; Alexander Saldanha (Great Lakes Symposium on VLSI, 1998)

Partial-scan delay fault testing of asynchronous circuits. - Michael Kishinevsky; Alex Kondratyev; Luciano Lavagno; Alexander Saldanha; Alexander Taubin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A methodology for correct-by-construction latency insensitive design. - Luca P. Carloni; Kenneth L. McMillan; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1999)

Functional timing optimization. - Alexander Saldanha (ICCAD, 1999)

Timing Analysis with Implicitly Specified False Paths. - Eugene Goldberg; Alexander Saldanha (VLSI Design, 2000)

FSM Encoding for BDD Representations. - Wilsin Gosti; Tiziano Villa; Alexander Saldanha; Alberto L. Sangiovanni-Vincentelli (Int. J. Appl. Math. Comput. Sci., 2007)