Delay Uncertainty Reduction by Interconnect and Gate Splitting. - Vineet Agarwal; Jin Sun 006; Alexander V. Mitev; Janet Meiling Wang (ASP-DAC, 2007)

Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method. - Alexander V. Mitev; Michael M. Marefat; Dongsheng Ma; Janet Meiling Wang (ASP-DAC, 2007)

A robust finite-point based gate model considering process variations. - Alexander V. Mitev; Dinesh Ganesan; Dheepan Shanmugasundaram; Yu Cao 001; Janet Meiling Wang (ICCAD, 2007)

Principle Hessian direction based parameter reduction with process variation. - Alexander V. Mitev; Michael M. Marefat; Dongsheng Ma; Janet Meiling Wang (ICCAD, 2007)

Finite-Point Gate Model for Fast Timing and Power Analysis. - Dinesh Ganesan; Alexander V. Mitev; Janet Meiling Wang; Yu Cao 001 (ISQED, 2008)

Parameter reduction for variability analysis by slice inverse regression method. - Alexander V. Mitev; Michael M. Marefat; Dongsheng Ma; Janet Meiling Wang (IET Circuits Devices Syst., 2008)

A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty. - Omar Hafiz; Alexander V. Mitev; Janet Meiling Wang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation. - Alexander V. Mitev; Michael M. Marefat; Dongsheng Ma; Janet Meiling Wang (IEEE Trans. Very Large Scale Integr. Syst., 2010)