40-Gb/s circuits built from a 120-GHz fT SiGe technology. - Greg G. Freeman; Mounir Meghelli; Young Kwark; Steven Zier; Alexander V. Rylyakov; Michael Sorna; Todd Tanji; Oswin M. Schreiber; Keith Walter; Jae-Sung Rieh; Basanth Jagannathan; Alvin J. Joseph; et al. (IEEE J. Solid State Circuits, 2002)

50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. - Mounir Meghelli; Alexander V. Rylyakov; Lei Shan (IEEE J. Solid State Circuits, 2002)

45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]. - Seongwon Kim; Mohit Kapur; Mounir Meghelli; Alexander V. Rylyakov; Young Hoon Kwark; Daniel J. Friedman (CICC, 2003)

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. - Woogeun Rhee; Herschel A. Ainspan; Sergey V. Rylov; Alexander V. Rylyakov; Michael P. Beakes; Daniel J. Friedman; Sudhir M. Gowda; Mehmet Soyuer (CICC, 2003)

SiGe BiCMOS integrated circuits for high-speed serial communication links. - Daniel J. Friedman; Mounir Meghelli; Benjamin D. Parker; Jungwook Yang; Herschel A. Ainspan; Alexander V. Rylyakov; Young Hoon Kwark; Mark B. Ritter; Lei Shan; Steven J. Zier; Michael Sorna; Mehmet Soyuer (IBM J. Res. Dev., 2003)

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems. - Mounir Meghelli; Alexander V. Rylyakov; Steven Zier; Michael Sorna; Daniel J. Friedman (IEEE J. Solid State Circuits, 2003)

96-GHz static frequency divider in SiGe bipolar technology. - Alexander V. Rylyakov; Thomas Zwick (IEEE J. Solid State Circuits, 2004)

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. - Behnam Analui; Alexander V. Rylyakov; Sergey V. Rylov; Mounir Meghelli; Ali Hajimiri (IEEE J. Solid State Circuits, 2005)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. - Alexander V. Rylyakov; José A. Tierno; George English; Daniel J. Friedman; M. Megheli (ISSCC, 2007)

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. - Azita Emami-Neyestanak; Aida Varzaghani; John F. Bulzacchelli; Alexander V. Rylyakov; Chih-Kong Ken Yang; Daniel J. Friedman (IEEE J. Solid State Circuits, 2007)

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. - Jackie Koon Lun Wong; Alexander V. Rylyakov; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2007)

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. - Alexander V. Rylyakov; José A. Tierno; George English; Michael A. Sperling; Daniel J. Friedman (CICC, 2008)

A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. - Alexander V. Rylyakov; José A. Tierno; Didem Zeliha Turker; Jean-Olivier Plouchart; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2008)

A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects. - Clint Schow; Fuad E. Doany; Chen Chen; Alexander V. Rylyakov; Christian W. Baks; Daniel M. Kuchta; Richard A. John; Jeffrey A. Kash (ISSCC, 2008)

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. - José A. Tierno; Alexander V. Rylyakov; Daniel J. Friedman (IEEE J. Solid State Circuits, 2008)

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. - Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Jean-Olivier Plouchart; John F. Bulzacchelli; Zeynep Toprak Deniz; Daniel J. Friedman (ISSCC, 2009)

Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link. - Clint L. Schow; Fuad E. Doany; Chen Chen; Alexander V. Rylyakov; Christian W. Baks; Daniel M. Kuchta; Richard A. John; Jeffrey A. Kash (IEEE J. Solid State Circuits, 2009)

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. - Montek Singh; José A. Tierno; Alexander V. Rylyakov; Sergey V. Rylov; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers. - Solomon Assefa; William M. J. Green; Alexander V. Rylyakov; Clint Schow; Folkert Horst; Yurii A. Vlasov (ACM Great Lakes Symposium on VLSI, 2011)

A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver. - Alexander V. Rylyakov; Clint Schow; Benjamin G. Lee; William M. J. Green; Joris Van Campenhout; Min Yang; Fuad E. Doany; Solomon Assefa; Christopher V. Jahnes; Jeffrey A. Kash; Yurii A. Vlasov (ISSCC, 2011)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (CICC, 2012)

25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS. - Jonathan E. Proesel; Clint Schow; Alexander V. Rylyakov (ISSCC, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (VLSIC, 2012)

Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links [Invited]. - Jonathan E. Proesel; Benjamin G. Lee; Alexander V. Rylyakov; Christian W. Baks; Clint L. Schow (JOCN, 2012)

Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers. - Alexander V. Rylyakov; Clint Schow; Benjamin G. Lee; William M. J. Green; Solomon Assefa; Fuad E. Doany; Min Yang; Joris Van Campenhout; Christopher V. Jahnes; Jeffrey A. Kash; Yurii A. Vlasov (IEEE J. Solid State Circuits, 2012)

Optical receivers using DFE-IIR equalization. - Jonathan E. Proesel; Alexander V. Rylyakov; Clint Schow (ISSCC, 2013)

Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node. - Solomon Assefa; Huapu Pan; Steven Shank; William M. J. Green; Alexander V. Rylyakov; Clint Schow; Marwan Khater; Swetha Kamlapurkar; Edward Kiewra; Carol Reinholm; Teya Topuria; Philip Rice; et al. (OFC/NFOEC, 2013)

A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link. - Daniel M. Kuchta; Clint L. Schow; Alexander V. Rylyakov; Jonathan E. Proesel; Fuad E. Doany; Christian W. Baks; B. H. Hamel-Bissell; Chris Kocot; L. Graham; R. Johnson; Gary Landry; E. Shaw; et al. (OFC/NFOEC, 2013)

Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits. - Benjamin G. Lee; Alexander V. Rylyakov; William M. J. Green; Solomon Assefa; Christian W. Baks; Renato Rimolo-Donadio; Daniel M. Kuchta; Marwan H. Khater; Tymon Barwicz; Carol Reinholm; Edward Kiewra; Steven M. Shank; et al. (OFC/NFOEC, 2013)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

Exploring the limits of high-speed receivers for multimode VCSEL-based optical links. - Nicolas Dupuis; Daniel M. Kuchta; Fuad E. Doany; Alexander V. Rylyakov; Jonathan E. Proesel; Christian W. Baks; Clint L. Schow; S. Luong; C. Xie; L. Wang; S. Huang; K. Jackson; et al. (OFC, 2014)

30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits. - Nicolas Dupuis; Benjamin G. Lee; Jonathan E. Proesel; Alexander V. Rylyakov; Renato Rimolo-Donadio; Christian W. Baks; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Robert S. Guzzon; Brian R. Koch; Daniel K. Sparacin; et al. (OFC, 2014)

Low power CMOS-driven 1060 nm multimode optical link. - Jean Benoit Héroux; Tomofumi Kise; Masaki Funabashi; Toyohiro Aoki; Clint Schow; Alexander V. Rylyakov; Shigeru Nakagawa (OFC, 2014)

64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL. - Daniel M. Kuchta; Alexander V. Rylyakov; Clint L. Schow; Jonathan E. Proesel; Christian W. Baks; Petter Westbergh; Johan S. Gustavsson; Anders Larsson (OFC, 2014)

A 28 GHz Hybrid PLL in 32 nm SOI CMOS. - Mark A. Ferriss; Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Daniel J. Friedman (IEEE J. Solid State Circuits, 2014)

A Throughput-Optimized Optical Network for Data-Intensive Computing. - Laurent Schares; Benjamin G. Lee; Fabio Checconi; Russell A. Budd; Alexander V. Rylyakov; Nicolas Dupuis; Fabrizio Petrini; Clint Schow; Pablo Fuentes 001; Oliver Mattes; Cyriel Minkenberg (IEEE Micro, 2014)

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2015)

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (ISSCC, 2015)

A 4-λ, 40Gb/s/λ bandwidth extension of multimode fiber in the 850nm range. - Daniel M. Kuchta; Tam N. Huynh; Fuad E. Doany; Alexander V. Rylyakov; Clint L. Schow; Petar K. Pepeljugoski; D. Gazula; Edward Shaw; Jim Tatum (OFC, 2015)

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. - Benjamin G. Lee; Renato Rimolo-Donadio; Alexander V. Rylyakov; Jonathan E. Proesel; John F. Bulzacchelli; Christian W. Baks; Mounir Meghelli; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Jae-Hyuk Shin; Brian R. Koch; et al. (OFC, 2015)

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. - Anand Ramaswamy; Jonathan E. Roth; Erik J. Norberg; Robert S. Guzzon; Jae-Hyuk Shin; J. T. Imamura; Brian R. Koch; Daniel K. Sparacin; Gregory A. Fish; Benjamin G. Lee; Renato Rimolo-Donadio; Christian W. Baks; et al. (OFC, 2015)

High speed circuits for short reach optical communications. - Alexander V. Rylyakov (OFC, 2015)

A 25 Gb/s burst-mode receiver for low latency photonic switch networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Clint Schow; Mounir Meghelli (OFC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (IEEE J. Solid State Circuits, 2015)

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. - Mark A. Ferriss; Bodhisatwa Sadhu; Alexander V. Rylyakov; Herschel A. Ainspan; Daniel J. Friedman (ISSCC, 2016)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

A 34Gbaud Linear Transimpedance Amplifier with Automatic Gain Control for 200Gb/s DP-16QAM Optical Coherent Receivers. - Mostafa Gamal Ahmed; Tam N. Huynh; Christopher Williams 003; Yong Wang 026; Rahul Shringarpure; Reza Yousefi; Jose Roman; Noam Ophir; Alexander V. Rylyakov (OFC, 2018)

A Silicon Photonic Transceiver and Hybrid Tunable Laser for 64 Gbaud Coherent Communication. - Ari Novack; Matthew Streshinsky; Tam N. Huynh; Tal Galfsky; Hang Guan; Yang Liu 178; Yangjin Ma; Ruizhi Shi; Alexandre Horth; Yaojia Chen; Amir Hanjani; Jose Roman; et al. (OFC, 2018)

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. - Mostafa Gamal Ahmed; Mrunmay Talegaonkar; Ahmed Elkholy; Guanghua Shu; Ahmed Elmallah; Alexander V. Rylyakov; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter. - Abdelrahman H. Ahmed; Daihyun Lim; Abdellatif Elmoznine; Yangjin Ma; Tam N. Huynh; Christopher Williams 003; Leonardo Vera; Yang Liu 178; Ruizhi Shi; Matthew Streshinsky; Ari Novack; Ran Ding; et al. (ISSCC, 2019)

Monolithically-Integrated 50 Gbps 2pJ/bit Photoreceiver with Cherry-Hooper TIA in 250nm BiCMOS Technology. - Hector Andrade; Takako Hirokawa; Aaron Maharry; Alexander V. Rylyakov; Clint L. Schow; James F. Buckwalter (OFC, 2019)

An All-Silicon Transmitter with Co-Designed Modulator and DC-Coupled Driver. - Yangjin Ma; Christopher Williams 003; Mostafa Gamal Ahmed; Abdellatif Elmoznine; Daihyun Lim; Yang Liu 178; Ruizhi Shi; Tam N. Huynh; Jose Roman; Abdelrahman H. Ahmed; Leonardo Vera; Yaojia Chen; et al. (OFC, 2019)

34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers. - Mostafa Gamal Ahmed; Tam N. Huynh; Christopher Williams 003; Yong Wang 026; Pavan Kumar Hanumolu; Alexander V. Rylyakov (IEEE J. Solid State Circuits, 2019)

A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength. - Abdelrahman H. Ahmed; Abdellatif Elmoznine; Daihyun Lim; Yangjin Ma; Alexander V. Rylyakov; Sudip Shekhar (IEEE J. Solid State Circuits, 2020)

A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength. - Abdelrahman H. Ahmed; Leonardo Vera; Lorenzo Iotti; Ruizhi Shi; Sudip Shekhar; Alexander V. Rylyakov (IEEE J. Solid State Circuits, 2023)

802 Gbps Coherent Optical Sub-Assembly (COSA) based on a Coupling Modulated Silicon Ring Resonator. - X. Chen; A. Mistry; A. El Sayed; C. Williams; Lorenzo Iotti; A. Atef; Kishore Padmaraju; M. Malinowski; D. Che; Rafid A. Sukkar; Rick Younce; Alexandre Horth; et al. (BCICTS, 2024)