A Compiler-Assisted Cache Coherence Solution for Multiprcessors. - Alexander V. Veidenbaum (ICPP, 1986)

The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs. - Hoichi Cheong; Alexander V. Veidenbaum (ICS, 1987)

Stale Data Detection and Coherence Enforcement Using Flow Analysis. - Hoichi Cheong; Alexander V. Veidenbaum (ICPP (1), 1988)

Performance of a shared memory system for vector multiprocessors. - Stephen W. Turner; Alexander V. Veidenbaum (ICS, 1988)

A Cache Coherence Scheme With Fast Selective Invalidation. - Hoichi Cheong; Alexander V. Veidenbaum (ISCA, 1988)

A version control approach to Cache coherence. - Hoichi Cheong; Alexander V. Veidenbaum (ICS, 1989)

Compiler-directed data prefetching in multiprocessors with memory hierarchies. - Edward H. Gornish; Elana D. Granston; Alexander V. Veidenbaum (ICS, 1990)

Compiler-Directed Cache Management in Multiprocessors. - Hoichi Cheong; Alexander V. Veidenbaum (Computer, 1990)

Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. - Kyle A. Gallivan; William Jalby; Stephen W. Turner; Alexander V. Veidenbaum; Harry A. G. Wijshoff (ICPP (1), 1991)

An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. - Elana D. Granston; Alexander V. Veidenbaum (ICPP (2), 1991)

The Organization of the Cedar System. - Jeff Konicek; Tracy Tilton; Alexander V. Veidenbaum; Chuan-Qi Zhu; Edward S. Davidson; Ruppert A. Downing; Michael J. Haney; Manish Sharma; Pen-Chung Yew; P. Michael Farmwald; David J. Kuck; Daniel M. Lavery; et al. (ICPP (1), 1991)

A software coherence scheme with the assistance of directories. - Yung-Chin Chen; Alexander V. Veidenbaum (ICS, 1991)

Chief: A Parallel Simulation Environment for Parallel Systems. - John D. Bruner; Hoichi Cheong; Alexander V. Veidenbaum; Pen-Chung Yew (IPPS, 1991)

Comparison and analysis of software and directory coherence schemes. - Yung-Chin Chen; Alexander V. Veidenbaum (SC, 1991)

Detecting redundant accesses to array data. - Elana D. Granston; Alexander V. Veidenbaum (SC, 1991)

An Effective Write Policy for Software Coherence Schemes. - Yung-Chin Chen; Alexander V. Veidenbaum (SC, 1992)

Performance Evaluation of Memory Caches in Multiprocessors. - Yung-Chin Chen; Alexander V. Veidenbaum (ICPP (1), 1993)

The Cedar System and an Initial Performance Study. - David J. Kuck; Edward S. Davidson; Duncan H. Lawrie; Ahmed H. Sameh; Chuan-Qi Zhu; Alexander V. Veidenbaum; Jeff Konicek; Pen-Chung Yew; Kyle A. Gallivan; William Jalby; Harry A. G. Wijshoff; Randall Bramley; et al. (ISCA, 1993)

Scalability of the Cedar system. - Stephen W. Turner; Alexander V. Veidenbaum (SC, 1994)

On Shortest Path Routing in Single Stage Shuffle-Exchange Networks. - Sunil Kim; Alexander V. Veidenbaum (SPAA, 1995)

Combining flow and dependence analyses to expose redundant array accesses. - Elana D. Granston; Alexander V. Veidenbaum (Int. J. Parallel Program., 1995)

The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems. - Sunil Kim; Alexander V. Veidenbaum (IEEE PACT, 1997)

Stride-directed Prefetching for Secondary Caches. - Sunil Kim; Alexander V. Veidenbaum (ICPP, 1997)

Instruction Cache Prefetching Using Multilevel Branch Prediction. - Alexander V. Veidenbaum (ISHPC, 1997)

Retrospective: The Cedar System. - Alexander V. Veidenbaum; Pen-Chung Yew; David J. Kuck; Constantine D. Polychronopoulos; David A. Padua; Edward S. Davidson; Kyle A. Gallivan (25 Years ISCA: Retrospectives and Reprints, 1998)

Adapting cache line size to application behavior. - Alexander V. Veidenbaum; Weiyu Tang; Rajesh K. Gupta 001; Alexandru Nicolau; Xiaomei Ji (International Conference on Supercomputing, 1999)

Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors. - Alexander V. Veidenbaum; Qingbo Zhao; Abduhl Shameer (Int. J. High Speed Comput., 1999)

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors. - Edward H. Gornish; Alexander V. Veidenbaum (Int. J. Parallel Program., 1999)

Interconnection network organization and its impact on performance and cost in shared memory multiprocessors. - Sunil Kim; Alexander V. Veidenbaum (Parallel Comput., 1999)

Compiler-Directed Cache Line Size Adaptivity. - Dan Nicolaescu; Xiaomei Ji; Alexander V. Veidenbaum; Alexandru Nicolau; Rajesh K. Gupta 001 (Intelligent Memory Systems, 2000)

Compiler-Directed Cache Assist Adaptivity. - Xiaomei Ji; Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau; Rajesh K. Gupta 001 (ISHPC, 2000)

On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors. - Sunil Kim; Alexander V. Veidenbaum (J. Supercomput., 2000)

Guest Editor's Introduction. - Alexander V. Veidenbaum (Int. J. Parallel Program., 2001)

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. - Ana Azevedo; Ilya Issenin; Radu Cornea; Rajesh Gupta 001; Nikil D. Dutt; Alexander V. Veidenbaum; Alexandru Nicolau (DATE, 2002)

Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. - Weiyu Tang; Alexander V. Veidenbaum; Alexandru Nicolau; Rajesh K. Gupta 001 (ISHPC, 2002)

Low Energy Associative Data Caches for Embedded Systems. - Dan Nicolaescu; Alexander V. Veidenbaum; Alex Nicolau (Embedded Software for SoC, 2003)

Energy Aware Register File Implementation through Instruction Predecode. - José L. Ayala; Marisa Luisa López-Vallejo; Alexander V. Veidenbaum; Carlos A. Lopez (ASAP, 2003)

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (DATE, 2003)

Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. - Sudeep Pasricha; Alexander V. Veidenbaum (ICCD, 2003)

A Simple Low-Energy Instruction Wakeup Mechanism. - Marco Antonio Ramírez; Adrián Cristal; Alexander V. Veidenbaum; Luís Villa; Mateo Valero (ISHPC, 2003)

Reducing data cache energy consumption via cached load/store queue. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (ISLPED, 2003)

A Data Cache with Dynamic Mapping. - Paolo D'Alberto; Alexandru Nicolau; Alexander V. Veidenbaum (LCPC, 2003)

Guest Editors' Introduction: Application-Specific Microprocessors. - Alex Orailoglu; Alexander V. Veidenbaum (IEEE Des. Test Comput., 2003)

Power-Aware Compilation for Register File Energy Reduction. - José L. Ayala; Alexander V. Veidenbaum; Marisa Luisa López-Vallejo (Int. J. Parallel Program., 2003)

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. - Juan L. Aragón; Dan Nicolaescu; Alexander V. Veidenbaum; Ana-Maria Badulescu (DATE, 2004)

Low Energy, Highly-Associative Cache Design for Embedded Processors. - Alexander V. Veidenbaum; Dan Nicolaescu (ICCD, 2004)

A Content Aware Integer Register File Organization. - Rubén González 001; Adrián Cristal; Daniel Ortega; Alexander V. Veidenbaum; Mateo Valero (ISCA, 2004)

Caching Values in the Load Store Queue. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (MASCOTS, 2004)

An Optimized Front-End Physical Register File with Banking and Writeback Filtering. - Miquel Pericàs; Rubén González 001; Adrián Cristal; Alexander V. Veidenbaum; Mateo Valero (PACS, 2004)

A partitioned instruction queue to reduce instruction wakeup energy. - Marco Antonio Ramírez; Adrián Cristal; Mateo Valero; Alexander V. Veidenbaum; Luís Villa (Int. J. High Perform. Comput. Netw., 2004)

Guest Editor's Introduction: Application-Specific Processors. - Alexander V. Veidenbaum (IEEE Micro, 2004)

Energy-Effective Instruction Fetch Unit for Wide Issue Processors. - Juan L. Aragón; Alexander V. Veidenbaum (Asia-Pacific Computer Systems Architecture Conference, 2005)

High performance annotation-aware JVM for Java cards. - Ana Azevedo; Arun Kejariwal; Alexander V. Veidenbaum; Alexandru Nicolau (EMSOFT, 2005)

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. - Marco Antonio Ramírez; Adrián Cristal; Mateo Valero; Alexander V. Veidenbaum; Luís Villa (ICCD, 2005)

An asymmetric clustered processor based on value content. - Rubén González 001; Adrián Cristal; Miquel Pericàs; Mateo Valero; Alexander V. Veidenbaum (ICS, 2005)

Using a Way Cache to Improve Performance of Set-Associative Caches. - Dan Nicolaescu; Alexander V. Veidenbaum; Alexandru Nicolau (ISHPC, 2005)

Decoupled State-Execute Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Alexander V. Veidenbaum; Mateo Valero (ISHPC, 2005)

Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. - Paolo D'Alberto; Alexandru Nicolau; Alexander V. Veidenbaum; Rajesh K. Gupta 001 (IEEE Trans. Computers, 2005)

Challenges in exploitation of loop parallelism in embedded applications. - Arun Kejariwal; Alexander V. Veidenbaum; Alexandru Nicolau; Milind Girkar; Xinmin Tian; Hideki Saito 001 (CODES+ISSS, 2006)

Probablistic Self-Scheduling. - Milind Girkar; Arun Kejariwal; Xinmin Tian; Hideki Saito 001; Alexandru Nicolau; Alexander V. Veidenbaum; Constantine D. Polychronopoulos (Euro-Par, 2006)

Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. - Dan Nicolaescu; Babak Salamat; Alexander V. Veidenbaum (ICCD, 2006)

On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. - Arun Kejariwal; Xinmin Tian; Wei Li 015; Milind Girkar; Sergey Kozhukhov; Hideki Saito 001; Utpal Banerjee; Alexandru Nicolau; Alexander V. Veidenbaum; Constantine D. Polychronopoulos (ICS, 2006)

A simplified java bytecode compilation system for resource-constrained embedded processors. - Carmen Badea; Alexandru Nicolau; Alexander V. Veidenbaum (CASES, 2007)

Reducing leakage power in peripheral circuits of L2 caches. - Houman Homayoun; Alexander V. Veidenbaum (ICCD, 2007)

Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. - Jeff Furlong; Andrew Felch; Jayram Moorkanikara Nageswaran; Nikil D. Dutt; Alex Nicolau; Alexander V. Veidenbaum; Ashok Chandrashekar; Richard Granger (PARCO, 2007)

Tight analysis of the performance potential of thread speculation using spec CPU 2006. - Arun Kejariwal; Xinmin Tian; Milind Girkar; Wei Li 015; Sergey Kozhukhov; Utpal Banerjee; Alexandru Nicolau; Alexander V. Veidenbaum; Constantine D. Polychronopoulos (PPoPP, 2007)

Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. - Arun Kejariwal; Gerolf Hoflehner; Darshan Desai; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum (SIGMETRICS, 2007)

A predictive decode filter cache for reducing power consumption in embedded processors. - Weiyu Tang; Arun Kejariwal; Alexander V. Veidenbaum; Alexandru Nicolau (ACM Trans. Design Autom. Electr. Syst., 2007)

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. - Houman Homayoun; Mohammad A. Makhzan; Alexander V. Veidenbaum (CASES, 2008)

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. - Houman Homayoun; Sudeep Pasricha; Mohammad A. Makhzan; Alexander V. Veidenbaum (DAC, 2008)

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. - Houman Homayoun; Mohammad A. Makhzan; Alexander V. Veidenbaum (ICCD, 2008)

Adaptive techniques for leakage power management in L2 cache peripheral circuits. - Houman Homayoun; Alexander V. Veidenbaum; Jean-Luc Gaudiot (ICCD, 2008)

A Two-Level Load/Store Queue Based on Execution Locality. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Alexander V. Veidenbaum; Daniel A. Jiménez; Mateo Valero (ISCA, 2008)

Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. - Carmen Badea; Alexandru Nicolau; Alexander V. Veidenbaum (LCTES, 2008)

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. - Houman Homayoun; Sudeep Pasricha; Mohammad A. Makhzan; Alexander V. Veidenbaum (LCTES, 2008)

A distributed processor state management architecture for large-window processors. - Isidro Gonzalez; Marco Galluzzi; Alexander V. Veidenbaum; Marco Antonio Ramírez; Adrián Cristal; Mateo Valero (MICRO, 2008)

Cache-aware iteration space partitioning. - Arun Kejariwal; Alexandru Nicolau; Utpal Banerjee; Alexander V. Veidenbaum; Constantine D. Polychronopoulos (PPoPP, 2008)

A centralized cache miss driven technique to improve processor power dissipation. - Houman Homayoun; Mohammad A. Makhzan; Jean-Luc Gaudiot; Alexander V. Veidenbaum (ICSAMOS, 2008)

Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. - Arun Kejariwal; Alexander V. Veidenbaum; Alexandru Nicolau; Xinmin Tian; Milind Girkar; Hideki Saito 001; Utpal Banerjee (ICSAMOS, 2008)

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. - José Luis Ayala; Marisa López-Vallejo; Carlos A. López-Barrio; Alexander V. Veidenbaum (Int. J. Embed. Syst., 2008)

Optimizing CAM-based instruction cache designs for low-power embedded systems. - Juan L. Aragón; Alexander V. Veidenbaum (J. Syst. Archit., 2008)

Improving SDRAM access energy efficiency for low-power embedded systems. - Jelena Trajkovic; Alexander V. Veidenbaum; Arun Kejariwal (ACM Trans. Embed. Comput. Syst., 2008)

Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. - Arun Kejariwal; Alexandru Nicolau; Alexander V. Veidenbaum; Utpal Banerjee; Constantine D. Polychronopoulos (ICPP, 2009)

Synchronization optimizations for efficient execution on multi-cores. - Alexandru Nicolau; Guangqiang Li; Alexander V. Veidenbaum; Arun Kejariwal (ICS, 2009)

Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. - Jayram Moorkanikara Nageswaran; Nikil D. Dutt; Jeffrey L. Krichmar; Alex Nicolau; Alexander V. Veidenbaum (IJCNN, 2009)

Power-aware load balancing of large scale MPI applications. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero; Alexander V. Veidenbaum (IPDPS, 2009)

Performance Characterization of Itanium® 2-Based Montecito Processor. - Darshan Desai; Gerolf Hoflehner; Arun Kejariwal; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum; Cameron McNairy (SPEC Benchmark Workshop, 2009)

Cache-aware partitioning of multi-dimensional iteration spaces. - Arun Kejariwal; Alexandru Nicolau; Utpal Banerjee; Alexander V. Veidenbaum; Constantine D. Polychronopoulos (SYSTOR, 2009)

Brain Derived Vision Algorithm on High Performance Architectures. - Jayram Moorkanikara Nageswaran; Andrew Felch; Ashok Chandrasekhar; Nikil D. Dutt; Richard Granger; Alex Nicolau; Alexander V. Veidenbaum (Int. J. Parallel Program., 2009)

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. - Jayram Moorkanikara Nageswaran; Nikil D. Dutt; Jeffrey L. Krichmar; Alex Nicolau; Alexander V. Veidenbaum (Neural Networks, 2009)

On the exploitation of loop-level parallelism in embedded applications. - Arun Kejariwal; Alexander V. Veidenbaum; Alexandru Nicolau; Milind Girkar; Xinmin Tian; Hideki Saito 001 (ACM Trans. Embed. Comput. Syst., 2009)

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. - Houman Homayoun; Avesta Sasan; Aseem Gupta; Alexander V. Veidenbaum; Fadi J. Kurdahi; Nikil D. Dutt (Conf. Computing Frontiers, 2010)

Exploitation of nested thread-level speculative parallelism on multi-core systems. - Arun Kejariwal; Milind Girkar; Xinmin Tian; Hideki Saito 001; Alexandru Nicolau; Alexander V. Veidenbaum; Utpal Banerjee; Constantine D. Polychronopoulos (Conf. Computing Frontiers, 2010)

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. - Houman Homayoun; Aseem Gupta; Alexander V. Veidenbaum; Avesta Sasan; Fadi J. Kurdahi; Nikil D. Dutt (HiPEAC, 2010)

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. - Shahin Golshan; Eli Bozorgzadeh; Benjamin Carrión Schäfer; Kazutoshi Wakabayashi; Houman Homayoun; Alexander V. Veidenbaum (ISLPED, 2010)

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. - Houman Homayoun; Shahin Golshan; Eli Bozorgzadeh; Alexander V. Veidenbaum; Fadi J. Kurdahi (ISQED, 2010)

On the efficacy of call graph-level thread-level speculation. - Arun Kejariwal; Milind Girkar; Xinmin Tian; Hideki Saito 001; Alexandru Nicolau; Alexander V. Veidenbaum; Utpal Banerjee; Constantine D. Polychronopoulos (WOSP/SIPEW, 2010)

Pruning hardware evaluation space via correlation-driven application similarity analysis. - Rosario Cammarota; Arun Kejariwal; Paolo D'Alberto; Sapan Panigrahi; Alexander V. Veidenbaum; Alexandru Nicolau (Conf. Computing Frontiers, 2011)

On leakage power optimization in clock tree networks for ASICs and general-purpose processors. - Houman Homayoun; Shahin Golshan; Eli Bozorgzadeh; Alexander V. Veidenbaum; Fadi J. Kurdahi (Sustain. Comput. Informatics Syst., 2011)

Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. - Houman Homayoun; Avesta Sasan; Jean-Luc Gaudiot; Alexander V. Veidenbaum (IEEE Trans. Very Large Scale Integr. Syst., 2011)

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. - Houman Homayoun; Avesta Sasan; Alexander V. Veidenbaum; Hsin-Cheng Yao; Shahin Golshan; Payam Heydari (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Revisiting level-0 caches in embedded processors. - Nam Duong; Taesu Kim; Dali Zhao; Alexander V. Veidenbaum (CASES, 2012)

Selective search of inlining vectors for program optimization. - Rosario Cammarota; Arun Kejariwal; Debora Donato; Alexandru Nicolau; Alexander V. Veidenbaum (Conf. Computing Frontiers, 2012)

A fault tolerant self-scheduling scheme for parallel loops on shared memory systems. - Yizhuo Wang 001; Alexandru Nicolau; Rosario Cammarota; Alexander V. Veidenbaum (HiPC, 2012)

Just in Time Load Balancing. - Rosario Cammarota; Alexandru Nicolau; Alexander V. Veidenbaum (LCPC, 2012)

Improving Cache Management Policies Using Dynamic Reuse Distances. - Nam Duong; Dali Zhao; Taesu Kim; Rosario Cammarota; Mateo Valero; Alexander V. Veidenbaum (MICRO, 2012)

Optimizing Program Performance via Similarity, Using a Feature-Agnostic Approach. - Rosario Cammarota; Laleh Aghababaie Beni; Alexandru Nicolau; Alexander V. Veidenbaum (APPT, 2013)

On the Determination of Inlining Vectors for Program Optimization. - Rosario Cammarota; Alexandru Nicolau; Alexander V. Veidenbaum; Arun Kejariwal; Debora Donato; Mukund Madhugiri (CC, 2013)

Effective Evaluation of Multi-core Based Systems. - Rosario Cammarota; Laleh Aghababaie Beni; Alexandru Nicolau; Alexander V. Veidenbaum (ISPDC, 2013)

Temperature aware thread migration in 3D architecture with stacked DRAM. - Dali Zhao; Houman Homayoun; Alexander V. Veidenbaum (ISQED, 2013)

Compiler-Assisted, Selective Out-Of-Order Commit. - Nam Duong; Alexander V. Veidenbaum (IEEE Comput. Archit. Lett., 2013)

Multiple stream tracker: a new hardware stride prefetcher. - Taesu Kim; Dali Zhao; Alexander V. Veidenbaum (Conf. Computing Frontiers, 2014)

Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies. - Edward H. Gornish; Elana D. Granston; Alexander V. Veidenbaum (ICS 25th Anniversary, 2014)

A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms. - Yizhuo Wang 001; Laleh Aghababaie Beni; Alexandru Nicolau; Alexander V. Veidenbaum; Rosario Cammarota (NPC, 2014)

Dynamic-vector execution on a general purpose EDGE chip multiprocessor. - Milovan Duric; Oscar Palomar; Aaron Smith; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero; Doug Burger; Alexander V. Veidenbaum (ICSAMOS, 2014)

Preface. - Carlo Galuzzi; Alexander V. Veidenbaum (ICSAMOS, 2014)

WebRTCbench: a benchmark for performance assessment of webRTC implementations. - Sajjad Taheri; Laleh Aghababaie Beni; Alexander V. Veidenbaum; Alexandru Nicolau; Rosario Cammarota; Jianlin Qiu; Qiang Lu; Mohammad R. Haghighat (ESTIMedia, 2015)

Software fault tolerance for FPUs via vectorization. - Zhi Chen 001; Ryoichi Inagaki; Alexandru Nicolau; Alexander V. Veidenbaum (SAMOS, 2015)

SIMD-based soft error detection. - Zhi Chen 001; Alexandru Nicolau; Alexander V. Veidenbaum (Conf. Computing Frontiers, 2016)

Polygonal Iteration Space Partitioning. - Aniket Shivam; Alexandru Nicolau; Alexander V. Veidenbaum; Mario Mango Furnari; Rosario Cammarota (LCPC, 2016)

Data-rate-aware FPGA-based acceleration framework for streaming applications. - Siavash Rezaei; César-Alejandro Hernández-Calderón; Saeed Mirzamohammadi; Eli Bozorgzadeh; Alexander V. Veidenbaum; Alex Nicolau; Michael J. Prather (ReConFig, 2016)

Special issue on energy efficient multi-core and many-core systems, Part I. - Amir-Mohammad Rahmani; Pasi Liljeberg; José Luis Ayala; Hannu Tenhunen; Alexander V. Veidenbaum (J. Parallel Distributed Comput., 2016)

LORE: A loop repository for the evaluation of compilers. - Zhi Chen 001; Zhangxiaowen Gong; Justin Josef Szaday; David C. Wong 001; David A. Padua; Alexandru Nicolau; Alexander V. Veidenbaum; Neftali Watkinson; Zehra Sura; Saeed Maleki; Josep Torrellas; Gerald DeJong (IISWC, 2017)

Using Hardware Counters to Predict Vectorization. - Neftali Watkinson; Aniket Shivam; Zhi Chen 001; Alexander V. Veidenbaum; Alexandru Nicolau; Zhangxiaowen Gong (LCPC, 2017)

CAMFAS: A Compiler Approach to Mitigate Fault Attacks via Enhanced SIMDization. - Zhi Chen 001; Junjie Shen 001; Alex Nicolau; Alexander V. Veidenbaum; Nahid Farhady Ghalaty; Rosario Cammarota (IACR Cryptol. ePrint Arch., 2017)

Special issue on energy efficient multi-core and many-core systems, Part II. - Amir-Mohammad Rahmani; Pasi Liljeberg; José Luis Ayala; Hannu Tenhunen; Alexander V. Veidenbaum (J. Parallel Distributed Comput., 2017)

Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines. - Sajjad Taheri; Jin Heo; Payman Behnam; Jeffrey Chen; Alexander V. Veidenbaum; Alexandru Nicolau (FCCM, 2018)

New Opportunities for Compilers in Computer Security. - Junjie Shen 001; Zhi Chen 001; Nahid Farhady Ghalaty; Rosario Cammarota; Alexandru Nicolau; Alexander V. Veidenbaum (LCPC, 2018)

Towards an Achievable Performance for the Loop Nests. - Aniket Shivam; Neftali Watkinson; Alexandru Nicolau; David A. Padua; Alexander V. Veidenbaum (LCPC, 2018)

OpenCV.js: computer vision processing for the open web platform. - Sajjad Taheri; Alexander V. Veidenbaum; Alexandru Nicolau; Ningxin Hu; Mohammad R. Haghighat (MMSys, 2018)

An empirical study of the effect of source-level loop transformations on compiler stability. - Zhangxiaowen Gong; Zhi Chen 001; Justin Josef Szaday; David C. Wong 001; Zehra Sura; Neftali Watkinson; Saeed Maleki; David A. Padua; Alexander V. Veidenbaum; Alexandru Nicolau; Josep Torrellas (Proc. ACM Program. Lang., 2018)

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms. - Sajjad Taheri; Payman Behnam; Eli Bozorgzadeh; Alexander V. Veidenbaum; Alexandru Nicolau (FPGA, 2019)

Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance. - Gongjin Sun; Junjie Shen 001; Alexander V. Veidenbaum (IPDPS, 2019)

Teaching Parallel Computing and Dependence Analysis with Python. - Neftali Watkinson; Aniket Shivam; Alexandru Nicolau; Alexander V. Veidenbaum (IPDPS Workshops, 2019)

MCompiler: A Synergistic Compilation Framework. - Aniket Shivam; Alexandru Nicolau; Alexander V. Veidenbaum (CoRR, 2019)

NumbaSummarizer: A Python Library for Simplified Vectorization Reports. - Neftali Watkinson; Preston Tai; Alexandru Nicolau; Alexander V. Veidenbaum (IPDPS Workshops, 2020)

Class-Modeling of Septic Shock With Hyperdimensional Computing. - Neftali Watkinson; Tony Givargis; Victor Joe; Alexandru Nicolau; Alexander V. Veidenbaum (EMBC, 2021)

Detecting COVID-19 Related Pneumonia On CT Scans Using Hyperdimensional Computing. - Neftali Watkinson; Tony Givargis; Victor Joe; Alexandru Nicolau; Alexander V. Veidenbaum (EMBC, 2021)

Hyperdimensional hashing: a robust and efficient dynamic hash table. - Mike Heddes; Igor Nunes; Tony Givargis; Alexandru Nicolau; Alexander V. Veidenbaum (DAC, 2022)

GraphHD: Efficient graph classification using hyperdimensional computing. - Igor Nunes; Mike Heddes; Tony Givargis; Alexandru Nicolau; Alexander V. Veidenbaum (DATE, 2022)

A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAs. - Mihnea Chirila; Paolo D'Alberto; Hsin-Yu Ting; Alexander V. Veidenbaum; Alexandru Nicolau (ISQED, 2022)

Using Hyperdimensional Computing to Extract Features for the Detection of Type 2 Diabetes. - Neftali Watkinson; Divya Devineni; Victor Joe; Tony Givargis; Alexandru Nicolau; Alexander V. Veidenbaum (IPDPS Workshops, 2023)

DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication. - Igor Nunes; Mike Heddes; Pere Vergés; Danny Abraham; Alexander V. Veidenbaum; Alex Nicolau; Tony Givargis (KDD, 2023)

Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE. - Marc Titus Trifan; Alexandru Nicolau; Alexander V. Veidenbaum (IACR Cryptol. ePrint Arch., 2023)

Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures. - Mike Heddes; Igor Nunes; Pere Vergés; Denis Kleyko; Danny Abraham; Tony Givargis; Alexandru Nicolau; Alexander V. Veidenbaum (J. Mach. Learn. Res., 2023)

Hyperdimensional computing: a framework for stochastic computation and symbolic AI. - Mike Heddes; Igor Nunes; Tony Givargis; Alexandru Nicolau; Alexander V. Veidenbaum (J. Big Data, 2024)