Designing logic circuits for probabilistic computation in the presence of noise. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DAC, 2005)

Designing MRF based error correcting circuits for memory elements. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2006)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (IEEE Micro, 2006)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2007)

Thermally-induced soft errors in nanoscale CMOS circuits. - Hua Li; Joseph L. Mundy; William R. Patterson; Dimitrios Kazazis; Alexander Zaslavsky; R. Iris Bahar (NANOARCH, 2007)

Designing Nanoscale Logic Circuits Based on Markov Random Fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (J. Electron. Test., 2007)

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. - Pooya Jannaty; Florian C. Sabou; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2010)

Z2-FET used as 1-transistor high-speed DRAM. - Jing Wan; Cyrille Le Royer; Alexander Zaslavsky; Sorin Cristoloveanu (ESSDERC, 2012)

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. - Marco Donato; Fabio Cremona; Warren Jin 002; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky; Joseph L. Mundy (ACM Great Lakes Symposium on VLSI, 2012)

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2015)

A fast simulator for the analysis of sub-threshold thermal noise transients. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (DAC, 2016)

Design of Error-Resilient Logic Gates with Reinforcement Using Implications. - Xijing Han; Marco Donato; R. Iris Bahar; Alexander Zaslavsky; William R. Patterson (ACM Great Lakes Symposium on VLSI, 2016)

A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Optimization of Discrete Parameters Using the Adaptive Gradient Method and Directed Evolution. - Andrei Beinarovich; Sergey Stepanov; Alexander Zaslavsky (CoRR, 2024)