Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. - Alexandra Ferrerón-Labari; Marta Ortín-Obón; Darío Suárez Gracia; Jesús Alastruey-Benedé; Víctor Viñals Yúfera (ARCS, 2013)

Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. - Marta Ortín; Alexandra Ferreron; Jorge Albericio; Darío Suárez Gracia; María Villarroya-Gaudó; Cruz Izu; Víctor Viñals (INA-OCMC@HiPEAC, 2013)

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. - Alexandra Ferrerón-Labari; Darío Suárez Gracia; Jesús Alastruey-Benedé; Teresa Monreal Arnal; Víctor Viñals (SBAC-PAD, 2014)

Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. - Darío Suárez Gracia; Alexandra Ferrerón-Labari; Luis Montesano Del Campo; Teresa Monreal Arnal; Víctor Viñals Yúfera (ACM Trans. Archit. Code Optim., 2014)

Identifying representative regions of parallel HPC applications: a cross-architectural evaluation. - Alexandra Ferreron; Radhika Jagtap; Roxana Rusitoru (IISWC, 2016)

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. - Alexandra Ferrerón-Labari; Darío Suárez Gracia; Jesús Alastruey-Benedé; Teresa Monreal Arnal; Pablo Ibáñez 001 (IEEE Trans. Computers, 2016)

Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications. - Alexandra Ferreron; Radhika Jagtap; Sascha Bischoff; Roxana Rusitoru (ISPASS, 2017)

AISC: Approximate Instruction Set Computer. - Alexandra Ferreron; Jesús Alastruey-Benedé; Darío Suárez Gracia; Ulya R. Karpuzcu (CoRR, 2018)

A fault-tolerant last level cache for CMPs operating at ultra-low voltage. - Alexandra Ferrerón-Labari; Jesús Alastruey-Benedé; Darío Suárez Gracia; Teresa Monreal Arnal; Pablo Ibáñez-Marín; Víctor Viñals Yúfera (J. Parallel Distributed Comput., 2019)