Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification. - Ruping Cao; John Ferguson; Fabien Gays; Youssef Drissi; Alexandre Arriordaz; Ian O'Connor (VLSI-SoC, 2014)

LVS check for photonic integrated circuits: curvilinear feature extraction and validation. - Ruping Cao; Julien Billoudet; John Ferguson; Lionel Couder; John Cayo; Alexandre Arriordaz; Ian O'Connor (DATE, 2015)

ITAC: A complete 3D integration test platform. - Didier Lattard; Lucile Arnaud; Arnaud Garnier; Nicolas Bresson; Franck Bana; R. Segaud; Amadine Jouve; H. Jacquinot; Stéphane Moreau; Karim Azizi-Mourier; C. Chantre; Pascal Vivet; et al. (3DIC, 2016)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)