A 80 Mb/s low-power scalable turbo codec core. - Alexandre Giulietti; Bruno Bougard; Veerle Derudder; Steven Dupont; Jan-Willem Weijers; Liesbet Van der Perre (CICC, 2002)

A class of power efficient VLSI architectures for high speed turbo-decoding. - Bruno Bougard; Alexandre Giulietti; Liesbet Van der Perre; Francky Catthoor (GLOBECOM, 2002)

Memory Power Reduction for High-Speed Implementation of Turbo Codes. - Bruno Bougard; Liesbet Van der Perre; F. Maessen; Alexandre Giulietti; Veerle Derudder; Francky Catthoor (J. VLSI Signal Process., 2003)