SYCLops: A SYCL Specific LLVM to MLIR Converter. - Alexandre Singer; Frank Gao; Kai-Ting Amy Wang (IWOCL, 2022)

Tiling for DMA-Based Hardware Accelerators (WIP). - Alexandre Singer; Kai-Ting Amy Wang (LCTES, 2023)

Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism. - Alexandre Singer; Hang Yan 014; Guozheng Zhang; Mark C. Jeffrey; Mirjana Stojilovic; Vaughn Betz (ICFPT, 2024)