GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França (DSD, 2009)

A massively parallel hardware architecture for ray-tracing. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França (Int. J. High Perform. Syst. Archit., 2009)

A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (DSD, 2011)

Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (ICA3PP (2), 2011)

A parallel architecture for ray-tracing with an embedded intersection algorithm. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak (ISCAS, 2011)

Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (VECPAR, 2012)

A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak; Henk Corporaal (ICA3PP (1), 2013)

Efficient hardware implementation of Ray Tracing based on an embedded software for intersection computation. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França (J. Syst. Archit., 2013)

Hardware reuse in modern application-specific processors and accelerators. - Alexandre Solon Nery; Lech Józwiak; Menno Lindwer; Mauro Cocco; Nadia Nedjah; Felipe M. G. França (Microprocess. Microsystems, 2013)

Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. - Alexandre Solon Nery; Nadia Nedjah; Felipe M. G. França; Lech Józwiak (Microprocess. Microsystems, 2013)

A framework for automatic custom instruction identification on multi-issue ASIPs. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak; Henk Corporaal (INDIN, 2014)

Automatic complex instruction identification for efficient application mapping onto ASIPs. - Alexandre Solon Nery; Nadia Nedjah; Felipe Maia Galvão França; Lech Józwiak; Henk Corporaal (LASCAS, 2014)

Efficient Pathfinding Co-Processors for FPGAs. - Alexandre Solon Nery; Alexandre da Costa Sena; Leandro Soares Guedes (SBAC-PAD (Workshops), 2017)

Dataflow Programming for Stream Processing. - Marcos Paulo Rocha; Felipe M. G. França; Alexandre Solon Nery; Leandro Soares Guedes (SBAC-PAD (Workshops), 2017)

A Smart Disk for In-Situ Face Recognition. - Victor da Cruz Ferreira; Alexandre Solon Nery; Felipe Maia Galvão França (IPDPS Workshops, 2018)

Efficient A* Co-processor for Reconfigurable Gaming Devices. - Alexandre Solon Nery; Alexandre da Costa Sena (SBGames, 2018)

Hardware-Accelerated Similarity Search with Multi-Index Hashing. - Leandro Santiago de Araújo; Victor da Cruz Ferreira; Brunno Figueiroa Goldstein; Alexandre Solon Nery; Leandro Augusto Justen Marzulo; Sandip Kundu; Felipe Maia Galvão França (DASC/PiCom/DataCom/CyberSciTech, 2019)

A Re-Configurable Ray-Triangle Vector Accelerator for Emerging Fog Architectures. - Adrianno Sampaio; Alexandre da Costa Sena; Alexandre Solon Nery (IPDPS Workshops, 2019)

A Feasible FPGA Weightless Neural Accelerator. - Victor da Cruz Ferreira; Alexandre Solon Nery; Leandro A. J. Marzulo; Leandro Santiago 001; Diego Fonseca Pereira de Souza; Brunno F. Goldstein; Felipe M. G. França; Vladimir Castro Alves (ISCAS, 2019)

DTM@GPU: Characterizing and evaluating trace redundancy in GPU. - Leandro A. J. Marzulo; Alexandre da Costa Sena; Alexandre Solon Nery; Cristiana Bentes; Igor Machado Coelho; Maria Clicia Stelling de Castro; Saulo T. Oliveira; Tiago A. O. Alves; Felipe M. G. França (Concurr. Comput. Pract. Exp., 2019)

DF-DTM: Dynamic Task Memoization and reuse in dataflow. - Leandro Rouberte; Alexandre da Costa Sena; Alexandre Solon Nery; Leandro A. J. Marzulo; Tiago A. O. Alves; Felipe M. G. França (Concurr. Comput. Pract. Exp., 2019)

An efficient pathfinding system in FPGA for edge/fog computing. - Alexandre Solon Nery; Alexandre da Costa Sena; Leandro Soares Guedes (Int. J. Grid Util. Comput., 2019)

An optimised dataflow engine for GPGPU stream processing. - Marcos Paulo Rocha; Felipe M. G. França; Alexandre Solon Nery; Leandro Soares Guedes (Int. J. Grid Util. Comput., 2019)

Reliability Evaluation of Compressed Deep Learning Models. - Brunno F. Goldstein; Sudarshan Srinivasan; Dipankar Das 002; Kunal Banerjee 001; Leandro Santiago de Araújo; Victor da Cruz Ferreira; Alexandre Solon Nery; Sandip Kundu; Felipe M. G. França (LASCAS, 2020)

A Lightweight Error-Resiliency Mechanism for Deep Neural Networks. - Brunno F. Goldstein; Victor da Cruz Ferreira; Sudarshan Srinivasan; Dipankar Das 002; Alexandre Solon Nery; Sandip Kundu; Felipe M. G. França (ISQED, 2021)

A CPU-FPGA heterogeneous approach for biological sequence comparison using high-level synthesis. - Carlos Antônio Campos Jorge; Alexandre Solon Nery; Alba C. M. A. Melo; Alfredo Goldman (Concurr. Comput. Pract. Exp., 2021)

Enabling heterogeneous ray-tracing acceleration in edge/cloud architectures. - Adrianno Sampaio; Alexandre da Costa Sena; Alexandre Solon Nery (Concurr. Comput. Pract. Exp., 2021)

Preventing DNN Model IP Theft via Hardware Obfuscation. - Brunno F. Goldstein; Vinay C. Patil; Victor da Cruz Ferreira; Alexandre Solon Nery; Felipe M. G. França; Sandip Kundu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)