Modeling subthreshold SOI logic for static timing analysis. - Alexandre Valentian; Olivier Thomas; Andrei Vladimirescu; Amara Amara (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. - Alexandre Valentian; Edith Beigné (ESSCIRC, 2007)

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (ASYNC, 2008)

A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. - Edith Beigné; Fabien Clermidy; Sylvain Miermont; Alexandre Valentian; Pascal Vivet; S. Barasinski; F. Blisson; N. Kohli; S. Kumar (ESSCIRC, 2008)

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability. - Alexandre Valentian; Edith Beigné (IEEE J. Solid State Circuits, 2008)

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits. - Lionel Cadix; Alexis Farcy; Cédric Bermond; Christine Fuchs; Patrick Leduc; Maxime Rousseau; Myriam Assous; Alexandre Valentian; Julie Roullard; Elie Eid; Nicolas Sillon; Bernard Fléchet; et al. (3DIC, 2009)

An Asynchronous Power Aware and Adaptive NoC Based Circuit. - Edith Beigné; Fabien Clermidy; Hélène Lhermet; Sylvain Miermont; Yvain Thonnart; Xuan-Tu Tran; Alexandre Valentian; Didier Varreau; Pascal Vivet; Xavier Popon; Hugo Lebreton (IEEE J. Solid State Circuits, 2009)

Power Reduction of Asynchronous Logic Circuits Using Activity Detection. - Yvain Thonnart; Edith Beigné; Alexandre Valentian; Pascal Vivet (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. - Julien Le Coz; Philippe Flatresse; Sylvain Engels; Alexandre Valentian; Marc Belleville; Christine Raynaud; Damien Croain; Pascal Urard (ISSCC, 2011)

Design challenges for nano-scale devices. - Marc Belleville; Olivier Thomas; Alexandre Valentian; Fabien Clermidy (ESSDERC, 2012)

A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. - Dimitri Soussan; Alexandre Valentian; Sylvain Majcherczak; Marc Belleville (ICICDT, 2012)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

An efficient metric of setup time for pulsed flip-flops based on output transition time. - Sebastien Bernard; Alexandre Valentian; Marc Belleville; David Bol; Jean-Didier Legat (ICICDT, 2013)

Comparing CMOS-Based and NEMS-Based Adiabatic Logic Circuits. - Samer Houri; Alexandre Valentian; Hervé Fanet (RC, 2013)

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. - Bertrand Pelloux-Prayer; Alexandre Valentian; Bastien Giraud; Yvain Thonnart; Jean-Philippe Noel; Philippe Flatresse; Edith Beigné (VLSI-SoC, 2013)

Advanced technologies for brain-inspired computing. - Fabien Clermidy; Rodolphe Héliot; Alexandre Valentian; Christian Gamrat; Olivier Bichler; Marc Duranton; Bilel Belhadj; Olivier Temam (ASP-DAC, 2014)

The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators. - Bilel Belhadj; Alexandre Valentian; Pascal Vivet; Marc Duranton; Liqiang He; Olivier Temam (CASES, 2014)

Shadow-scan design with low latency overhead and in-situ slack-time monitoring. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Alexandre Valentian; Suresh Pajaniradja; Lirida Alves de Barros Naviner; Valentin Gherman (ETS, 2014)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. - Sebastien Bernard; Marc Belleville; Alexandre Valentian; Jean-Didier Legat; David Bol (PATMOS, 2014)

A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. - Sebastien Bernard; Alexandre Valentian; David Bol; Jean-Didier Legat; Marc Belleville (J. Low Power Electron., 2014)

UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. - Edith Beigné; Jean-Frédéric Christmann; Alexandre Valentian; Olivier Billoint; Esteve Amat; Dominique Morche (ESSDERC, 2015)

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits. - Samer Houri; Gérard Billiot; Marc Belleville; Alexandre Valentian; Hervé Fanet (RC, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. - Samer Houri; Gérard Billiot; Marc Belleville; Alexandre Valentian; Hervé Fanet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose. - Gerald Cibrario; Nour Ben Salem; Joris Lacord; Karim Azizi-Mourier; Olivier Rozeau; Etienne Maurin; Olivier Billoint; Sébastien Thuries; Alexandre Valentian (3DIC, 2016)

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. - Sebastien Bernard; Marc Belleville; Jean-Didier Legat; Alexandre Valentian; David Bol (Microelectron. J., 2016)

Architecture exploration of a fixed point computation unit using precise timing spiking neurons. - Thomas Mesquida; Alexandre Valentian; David Bol; Edith Beigné (PATMOS, 2017)

Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks. - Elisa Vianello; Denys R. B. Ly; Selina La Barbera; Thomas Dalgaty; Niccolo Castellani; Gabriele Navarro; Guillaume Bourgeois; Alexandre Valentian; Etienne Nowak; Damien Querlioz (ICECS, 2018)

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. - Pascal Vivet; Gilles Sicard; Laurent Millet; Stéphane Chevobbe; Karim Ben Chehida; Luis Angel Cubero; Monte Alegre; Maxence Bouvier; Alexandre Valentian; Maria Lepecq; Thomas Dombek; Olivier Bichler; et al. (DATE, 2019)

Spiking Neural Networks Hardware Implementations and Challenges: A Survey. - Maxence Bouvier; Alexandre Valentian; Thomas Mesquida; François Rummens; Marina Reyboz; Elisa Vianello; Edith Beigné (ACM J. Emerg. Technol. Comput. Syst., 2019)

Fully-Integrated Spiking Neural Network Using SiOx-Based RRAM as Synaptic Device. - Amir Regev; Alessandro Bricalli; Giuseppe Piccolboni; Alexandre Valentian; Thomas Mesquida; Gabriel Molas; Jean-François Nodin (AICAS, 2020)

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. - Ivan Miro Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Anthony Quelen; Emmanuel Pluchart; Jean-Philippe Noel; Reda Boumchedda; et al. (VLSI Circuits, 2020)

Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers. - Maxence Bouvier; Alexandre Valentian; Gilles Sicard (DAC, 2021)

Overcoming the Data Deluge Challenges with Greener Electronics. - Jean-René Léquepeys; Marc Duranton; Susana Bonnetier; Sandrine Catrou; Richard Fournel; Thomas Ernst 005; Laurent Hérault; D. Louis; A. Jerraya; Alexandre Valentian; François Perruchot; Thomas Signamarcheix; et al. (ESSDERC, 2021)

2021 Roadmap on Neuromorphic Computing and Engineering. - Dennis V. Christensen; Regina Dittmann; Bernabé Linares-Barranco; Abu Sebastian; Manuel Le Gallo; Andrea Redaelli; Stefan Slesazeck; Thomas Mikolajick; Sabina Spiga; Stephan Menzel; Ilia Valov; Gianluca Milano; et al. (CoRR, 2021)

Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (ICANN (3), 2022)

2022 roadmap on neuromorphic computing and engineering. - Dennis V. Christensen; Regina Dittmann; Bernabé Linares-Barranco; Abu Sebastian; Manuel Le Gallo; Andrea Redaelli; Stefan Slesazeck; Thomas Mikolajick; Sabina Spiga; Stephan Menzel; Ilia Valov; Gianluca Milano; et al. (Neuromorph. Comput. Eng., 2022)

Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting. - Manon Dampfhoffer; Thomas Mesquida; Emmanuel Hardy; Alexandre Valentian; Lorena Anghel (ICASSP, 2023)

Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses. - Manon Dampfhoffer; Joel Minguet Lopez; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IJCNN, 2023)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)

Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IEEE Trans. Emerg. Top. Comput. Intell., 2023)

A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. - Ivan Miro-Panades; Vincent Lorrain; Lilian Billod; Inna Kucher; Vincent Templier; Sylvain Choisnet; Nermine Ali; Baptiste Rossigneux; Olivier Bichler; Alexandre Valentian (APCCAS, 2024)

Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. - Ivan Miro-Panades; Vincent Lorrain; Lilian Billod; Inna Kucher; Vincent Templier; Sylvain Choisnet; Nermine Ali; Baptiste Rossigneux; Olivier Bichler; Alexandre Valentian (APCCAS, 2024)

Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey. - Manon Dampfhoffer; Thomas Mesquida; Alexandre Valentian; Lorena Anghel (IEEE Trans. Neural Networks Learn. Syst., 2024)