Metric Definition for Circuit Speed Optimization. - Xavier Michel; Alexandre Verle; Nadine Azémard; Philippe Maurine; Daniel Auvergne (PATMOS, 2003)

CMOS Gate Sizing under Delay Constraint. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2003)

Delay bound based CMOS gate sizing technique. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ISCAS (5), 2004)

Performance Metric Based Optimization Protocol. - Xavier Michel; Alexandre Verle; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Low Power Oriented CMOS Circuit Optimization Protocol. - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (DATE, 2005)

Circuit optimization based on speed indicators. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (ICECS, 2005)

Speed Indicators for Circuit Optimization. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (PATMOS, 2005)

Circuit sizing method under delay constraint. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (ISCAS, 2006)