Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits. - Oana Boncalo; Mihai Udrescu; Lucian Prodan; Mircea Vladutiu; Alexandru Amaricai (Annual Simulation Symposium, 2007)

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. - Alexandru Amaricai; Mircea Vladutiu; Lucian Prodan; Mihai Udrescu; Oana Boncalo (DDECS, 2007)

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. - Alexandru Amaricai; Mircea Vladutiu; Lucian Prodan; Mihai Udrescu; Oana Boncalo (DSD, 2007)

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. - Oana Boncalo; Mihai Udrescu; Lucian Prodan; Mircea Vladutiu; Alexandru Amaricai (DSD, 2007)

Assessing quantum circuits reliability with mutant-based simulated fault injection. - Oana Boncalo; Mihai Udrescu; Lucian Prodan; Mircea Vladutiu; Alexandru Amaricai (ECCTD, 2007)

Simulated Fault Injection for Quantum Circuits Based on Simulator Commands. - Oana Boncalo; Mihai Udrescu; Lucian Prodan; Mircea Vladutiu; Alexandru Amaricai (SACI, 2007)

Floating point multiplication rounding schemes for interval arithmetic. - Alexandru Amaricai; Mircea Vladutiu; Mihai Udrescu; Lucian Prodan; Oana Boncalo (ASAP, 2008)

A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units. - Virgil E. Petcu; Alexandru Amaricai; Mircea Vladutiu (DDECS, 2008)

Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. - Alexandru Amaricai; Oana Boncalo (DSD, 2009)

Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. - Oana Boncalo; Alexandru Amaricai (DSD, 2009)

Quantum circuit's reliability assessment with VHDL-based simulated fault injection. - Oana Boncalo; Alexandru Amaricai; Mihai Udrescu; Mircea Vladutiu (Microelectron. Reliab., 2010)

Design Issues and Implementations for Floating-Point Divide-Add Fused. - Alexandru Amaricai; Mircea Vladutiu; Oana Boncalo (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator. - Alexandru Amaricai; Alin Dobre; Oana Boncalo; Andrei V. Tanase; Camelia Valuch (SACI, 2011)

FPGA implementation of very high radix square root with prescaling. - Alexandru Amaricai; Oana Boncalo (ICECS, 2012)

Automatic Generation of FPGA Hardware Accelerators for Graphics Applications. - Alexandru Amaricai; Oana Boncalo (PECCS, 2012)

A cycle-count-accurate simulation platform with enhanced design exploration capability. - Oana Boncalo; Alin Dobre; Alexandru Amaricai; Andrei V. Tanase (SimuTools, 2012)

FPGA implementation of hybrid fixed point - Floating point multiplication. - Alexandru Amaricai; Oana Boncalo; Ovidiu Sicoe; Marius Marcu (MIXDES, 2013)

SRT radix-2 dividers with (5, 4) redundant representation of partial remainder. - Alexandru Amaricai; Oana Boncalo (NORCHIP, 2013)

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits. - Alexandru Amaricai; Sergiu Nimara; Oana Boncalo; Jiaoyan Chen 002; Emanuel M. Popovici (DSD, 2014)

An FPGA sliding window-based architecture harris corner detector. - Alexandru Amaricai; Constantina-Elena Gavriliu; Oana Boncalo (FPL, 2014)

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing. - Oana Boncalo; Alexandru Amaricai; Andrei Hera; Valentin Savin (FPL, 2014)

Memory efficient implementation of self-corrected min-sum LDPC decoder. - Oana Boncalo; Alexandru Amaricai; Valentin Savin (ICECS, 2014)

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits. - Jiaoyan Chen 002; Christian Spagnol; Satish Grandhi; Emanuel M. Popovici; Sorin Cotofana; Alexandru Amaricai (ISVLSI, 2014)

Cost effective FPGA probabilistic fault emulation. - Oana Boncalo; Alexandru Amaricai; Christian Spagnol; Emanuel M. Popovici (NORCHIP, 2014)

Energy profiling of FPGA designs. - Cosmin Cernazanu-Glavan; Stefan Fedeac; Alexandru Amaricai-Boncalo; Marius Marcu (ROSE, 2014)

Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays. - Alexandru Amaricai; Oana Boncalo; Constantina-Elena Gavriliu (IET Comput. Digit. Tech., 2014)

Template-based QC-LDPC decoder architecture generation. - Oana Boncalo; Petru Florin Mihancea; Alexandru Amaricai (ICICS, 2015)

Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques. - Ioana Mot; Oana Boncalo; Alexandru Amaricai (DDECS, 2015)

Direct FPGA-based power profiling for a RISC processor. - Cosmin Cernazanu-Glavan; Marius Marcu; Alexandru Amaricai; Stefan Fedeac; Madalin Ghenea; Zheng Wang 027; Anupam Chattopadhyay; Jan Weinstock; Rainer Leupers (I2MTC, 2015)

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. - Andrei Hera; Oana Boncalo; Constantina-Elena Gavriliu; Alexandru Amaricai; Valentin Savin; David Declercq; Fakhreddine Ghaffari (MIXDES, 2015)

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. - Truong Nguyen-Ly; Khoa Le; Fakhreddine Ghaffari; Alexandru Amaricai; Oana Boncalo; Valentin Savin; David Declercq (NEWCAS, 2015)

Sub-threshold CMOS circuits reliability assessment using simulated fault injection based on simulator commands. - Sergiu Nimara; Alexandru Amaricai; Mircea Popa 001 (SACI, 2015)

Generation of floating point 2D translation operators for FPGA. - Ovidiu Sicoe; Alexandru Amaricai; Mircea Popa 001 (SACI, 2015)

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting. - Marius Marcu; Oana Boncalo; Madalin Ghenea; Alexandru Amaricai; Jan Weinstock; Rainer Leupers; Zheng Wang 027; Giorgis Georgakoudis; Dimitrios S. Nikolopoulos; Cosmin Cernazanu-Glavan; Lucian Bara; Marian Ionascu (ARCS, 2016)

FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization. - Sergiu Nimara; Oana Boncalo; Alexandru Amaricai; Mircea Popa 001 (DDECS, 2016)

Reliability analysis of memory centric LDPC decoders under probabilistic storage failures. - Alexandru Amaricai; Sergiu Nimara; Oana Boncalo; Emanuel M. Popovici (ICECS, 2016)

Configurable FPGA architecture for hardware-software merge sorting. - Patricia Carla Petrut; Alexandru Amaricai; Oana Boncalo (MIXDES, 2016)

Variable throughput LDPC decoders using SIMD-based adaptive quantization. - Virgil E. Petcu; Oana Boncalo; Alexandru Amaricai; Valentin Savin (TSP, 2016)

Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders. - Oana Boncalo; Alexandru Amaricai (ISVLSI, 2017)

Unrolled layered architectures for non-surjective finite alphabet iterative decoders. - Oana Boncalo; Valentin Savin; Alexandru Amaricai (NORCAS, 2017)

On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers. - Alexandru Amaricai; Ovidiu Sicoe; Oana Boncalo (J. Circuits Syst. Comput., 2017)

Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding. - Oana Boncalo; Alexandru Amaricai; Sergiu Nimara (DSD, 2018)

Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller. - Oana Boncalo; Alexandru Amaricai; Zsófia Lendek (DSD, 2019)

A Log-Likelihood Ratio based Generalized Belief Propagation. - Alexandru Amaricai; Mohsen Bahrami; Bane Vasic (EUROCON, 2019)

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation. - Oana Boncalo; Gyorgy Kolumban-Antal; Alexandru Amaricai; Valentin Savin; David Declercq (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Layered LDPC decoder in-order message access scheduling: a case study. - Oana Boncalo; Alexandru Amaricai (SACI, 2020)

Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes. - Oana Boncalo; Alexandru Amaricai (DFT, 2023)

Iterative Gradient Descent Decoding for Real Number LDPC Codes. - Oana Boncalo; Alexandru Amaricai (CoRR, 2024)