Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool. - Christophe Alias; Alain Darte; Alexandru Plesco (ASAP, 2010)

Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. (Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels). - Alexandru Plesco (2010)

Automatic Generation of FPGA-Specific Pipelined Accelerators. - Christophe Alias; Bogdan Pasca 001; Alexandru Plesco (ARC, 2011)

An FPGA architecture for solving the Table Maker's Dilemma. - Florent de Dinechin; Jean-Michel Muller; Bogdan Pasca 001; Alexandru Plesco (ASAP, 2011)

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA. - Christophe Alias; Alain Darte; Alexandru Plesco (PPoPP, 2012)

FPGA-specific synthesis of loop-nests with pipelined computational cores. - Christophe Alias; Bogdan Pasca 001; Alexandru Plesco (Microprocess. Microsystems, 2012)

Optimizing Affine Control With Semantic Factorizations. - Christophe Alias; Alexandru Plesco (ACM Trans. Archit. Code Optim., 2017)

Data-aware process networks. - Christophe Alias; Alexandru Plesco (CC, 2021)