Transistor reordering for low power CMOS gates using an SP-BDD representation. - Alexey Glebov; David T. Blaauw; Larry G. Jones (ISLPD, 1995)

Fast power loss calculation for digital static CMOS circuits. - Sergey Gavrilov; Alexey Glebov; Sergey G. Rusakov; David T. Blaauw; Larry G. Jones; Gopalakrishnan Vijayan (ED&TC, 1997)

Library-less synthesis for static CMOS combinational logic circuits. - Sergey Gavrilov; Alexey Glebov; Satyamurthy Pullela; S. C. Moore; Abhijit Dharchoudhury; Rajendran Panda; Gopalakrishnan Vijayan; David T. Blaauw (ICCAD, 1997)

False-Noise Analysis using Logic Implications. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Supamas Sirichotiyakul; Chanhee Oh; Vladimir Zolotov (ICCAD, 2001)

False-Noise Analysis Using Resolution Method. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Vladimir Zolotov; Rajendran Panda; Chanhee Oh (ISQED, 2002)

False-noise analysis using logic implications. - Alexey Glebov; Sergey Gavrilov; David T. Blaauw; Vladimir Zolotov (ACM Trans. Design Autom. Electr. Syst., 2002)

SOI Transistor Model for Fast Transient Simulation. - D. Nadezhin; Sergey Gavrilov; Alexey Glebov; Y. Egorov; Vladimir Zolotov; David T. Blaauw; Rajendran Panda; Murat R. Becer; Alexandre Ardelea; A. Patel (ICCAD, 2003)

False-Noise Analysis for Domino Circuits. - Alexey Glebov; Sergey Gavrilov; Vladimir Zolotov; Chanhee Oh; Rajendran Panda; Murat R. Becer (DATE, 2004)

Delay noise pessimism reduction by logic correlations. - Alexey Glebov; Sergey Gavrilov; R. Soloviev; Vladimir Zolotov; Murat R. Becer; Chanhee Oh; Rajendran Panda (ICCAD, 2004)

Calculation of stress probability for NBTI-aware timing analysis. - Alexander L. Stempkovsky; Alexey Glebov; Sergey Gavrilov (ISQED, 2009)