Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. - Manuel Sellier; Jean-Michel Portal; Bertrand Borot; Steve Colquhoun; Richard Ferrant; Frédéric Boeuf; Alexis Farcy (ISQED, 2008)

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits. - Lionel Cadix; Alexis Farcy; Cédric Bermond; Christine Fuchs; Patrick Leduc; Maxime Rousseau; Myriam Assous; Alexandre Valentian; Julie Roullard; Elie Eid; Nicolas Sillon; Bernard Fléchet; et al. (3DIC, 2009)

Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking. - Elie Eid; Thierry Lacrevaz; Sébastien de Rivaz; Cédric Bermond; Bernard Fléchet; Françis Calmon; Christian Gontrand; Alexis Farcy; Lionel Cadix; Pascal Ancey (3DIC, 2009)

First integration of Cu TSV using die-to-wafer direct bonding and planarization. - Patrick Leduc; Myriam Assous; Léa Di Cioccio; Marc Zussy; Thomas Signamarcheix; Antonio Roman; Maxime Rousseau; Sophie Verrun; Laurent Bally; David Bouchu; Lionel Cadix; Alexis Farcy; et al. (3DIC, 2009)

Influence of 3D integration on 2D interconnections and 2D self inductors HF properties. - Julie Roullard; Stéphane Capraro; Thierry Lacrevaz; Lionel Cadix; Elie Eid; Alexis Farcy; Bernard Fléchet (3DIC, 2009)

3D integration demonstration of a wireless product with design partitioning. - G. Druais; Pascal Ancey; C. Aumont; V. Caubet; Laurent-Luc Chapelon; C. Chaton; Séverine Cheramy; S. Cordova; E. Cirot; Jean-Philippe Colonna; Perceval Coudrain; T. Divel; et al. (3DIC, 2011)

Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix. - Patrick Le Maitre; Melanie Brocard; Alexis Farcy; Jean-Claude Marin (ISQED, 2012)

RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. - Melanie Brocard; Cédric Bermond; Thierry Lacrevaz; Alexis Farcy; Patrick Le Maitre; P. Scheer; Patrick Leduc; Séverine Cheramy; Bernard Fléchet (3DIC, 2013)

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. - Sylvain Joblot; Alexis Farcy; Nicolas Hotellier; Amadine Jouve; François de Crecy; Arnaud Garnier; M. Argoud; C. Ferrandon; J.-P. Colonna; R. Franiatte; C. Laviron; Séverine Cheramy (3DIC, 2013)

Thermal correlation between measurements and FEM simulations in 3D ICs. - Papa Momar Souare; François de Crecy; Vincent Fiori; M. Haykel Ben Jamaa; Alexis Farcy; Sébastien Gallois-Garreignot; Andras Borbely; Jean-Philippe Colonna; Perceval Coudrain; B. Giraud; C. Laviron; Séverine Cheramy; et al. (3DIC, 2013)

Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments. - Benjamin Vianne; Pierre Bar; Vincent Fiori; Sebastien Petitdidier; Norbert Chevrier; Sébastien Gallois-Garreignot; Alexis Farcy; Pascal Chausse; Stéphanie Escoubas; Nicolas Hotellier; Olivier Thomas (3DIC, 2013)

Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer. - Khadim Dieng; Philippe Artillan; Cédric Bermond; Olivier Guiller; Thierry Lacrevaz; Sylvain Joblot; Gregory Houzet; Alexis Farcy; Yann Lamy; Bernard Fléchet (3DIC, 2014)

Using TSVs for thermal mitigation in 3D circuits: Wish and truth. - Cristiano Santos; Papa Momar Souare; François de Crecy; Perceval Coudrain; Jean-Philippe Colonna; Pascal Vivet; Andras Borbely; Ricardo Reis 001; M. Haykel Ben Jamaa; Vincent Fiori; Alexis Farcy (3DIC, 2014)

EUROSERVER: Energy Efficient Node for European Micro-Servers. - Yves Durand; Paul M. Carpenter; Stefano Adami; Angelos Bilas; Denis Dutoit; Alexis Farcy; Georgi Gaydadjiev; John Goodacre; Manolis Katevenis; Manolis Marazakis; Emil Matús; Iakovos Mavroidis; et al. (DSD, 2014)

Stress management strategy to limit die curvature during silicon interposer integration. - Benjamin Vianne; Alexis Farcy; Vincent Fiori; Cédrick Chappaz; Norbert Chevrier; G. Lobascio; Pascal Chausse; F. Ponthenier; A. Ruckly; Stéphanie Escoubas; Olivier Thomas (3DIC, 2015)

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform. - Frédéric Boeuf; Sebastien Cremer; Enrico Temporiti; Massimo Fere; Mark Shaw 002; Nathalie Vulliet; Bastien Orlando; Delia Ristoiu; Alexis Farcy; Thierry Pinguet; Attila Mekis; Gianlorenzo Masini; et al. (OFC, 2015)

Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence. - Simon Gousseau; Stéphane Moreau; David Bouchu; Alexis Farcy; Pierre Montmitonnet; Karim Inal; François Bay; Marc Zelsmann; Emmanuel Picard; Mathieu Salaün (Microelectron. Reliab., 2015)

ITAC: A complete 3D integration test platform. - Didier Lattard; Lucile Arnaud; Arnaud Garnier; Nicolas Bresson; Franck Bana; R. Segaud; Amadine Jouve; H. Jacquinot; Stéphane Moreau; Karim Azizi-Mourier; C. Chantre; Pascal Vivet; et al. (3DIC, 2016)

Heat spreading packaging solutions for hybrid bonded 3D-ICs. - Rafael Prieto; Perceval Coudrain; Jean-Philippe Colonna; Y. Hallez; Christian Chancel; Venceslass Rat; Sylvain Dumas; G. Romano; R. Franiatte; C. Brunet-Manquiat; Séverine Cheramy; Alexis Farcy (3DIC, 2016)

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. - Perceval Coudrain; Papa Momar Souare; Rafael Prieto; Vincent Fiori; Alexis Farcy; Laurent Le Pailleur; Jean-Philippe Colonna; Cristiano Santos; Pascal Vivet; M. Haykel Ben Jamaa; Denis Dutoit; François de Crecy; et al. (IEEE Des. Test, 2016)

Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability. - Lucile Arnaud; Stéphane Moreau; Amadine Jouve; Imed Jani; Didier Lattard; F. Fournel; C. Euvrard; Y. Exbrayat; Viorel Balan; Nicolas Bresson; S. Lhostis; J. Jourdon; et al. (IRPS, 2018)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)