Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. - Alexis Landrault; Ludovic Pellier; Alexandre Richard; Christian Jay; Michel Robert; Daniel Auvergne (PATMOS, 2002)

Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach. - Jean-Pierre Dérutin; Lionel Damez; Alexis Landrault (ACIVS, 2008)

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach. - Lionel Damez; Loïc Siéler; Alexis Landrault; Jean-Pierre Dérutin (J. Real Time Image Process., 2011)

Teaching advanced digital ASIC designs by a complex case study. - Mohamed Amine Boussadi; Thierry Tixier; Alexis Landrault; Jean-Pierre Dérutin (EWME, 2014)

A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications. - Mohamed Amine Boussadi; Thierry Tixier; Alexis Landrault; Jean-Pierre Dérutin (MWSCAS, 2014)

HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms. - Mohamed Amine Boussadi; Thierry Tixier; Alexis Landrault; Jean-Pierre Dérutin (ReCoSoC, 2014)

Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods. - Frantz Pelissier; Hanen Chenini; François Berry; Alexis Landrault; Jean-Pierre Dérutin (J. Real Time Image Process., 2016)

HNCP: A many-core microprocessor ASIC approach dedicated to embedded image processing applications. - Mohamed Amine Boussadi; Thierry Tixier; Alexis Landrault; Jean-Pierre Dérutin (Microprocess. Microsystems, 2016)

Domain Adaptation for Pedestrian DCNN Detector toward a Specific Scene and an Embedded Platform. - Nada Hammami; Ala Mhalla; Alexis Landrault (VISIGRAPP (5: VISAPP), 2019)