Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. - Alexis Ramos; Juan Antonio Maestro; Pedro Reviriego (Microelectron. Reliab., 2017)

Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. - Alexis Ramos; Anees Ullah; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2018)

An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs. - Alexis Ramos; Ricardo Gonzalez-Toral; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Computers, 2019)

Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. - Imran Wali; Alfonso Sánchez-Macián; Alexis Ramos; Juan Antonio Maestro (ICECS, 2020)

Very Low Latency Architecture for Earth Observation Satellite Onboard Data Handling, Compression, and Encryption. - Michele Caon; Paolo Motto Ros; Maurizio Martina; Tiziano Bianchi; Enrico Magli; Francisco Membibre; Alexis Ramos; Antonio Latorre; Murray Kerr; Stefan Wiehle; Helko Breit; Dominik Günzel; et al. (IGARSS, 2021)

EO-Alert: A Satellite Architecture for Detection and Monitoring of Extreme Events in Real Time. - Murray Kerr; Stefania Tonetti; Stefania Carnara; Juan Ignacio Bravo; Robert Hinz; Antonio Latorre; Francisco Membibre; Alexis Ramos; Stefan Wiehle; Otto Koudelka; Enrico Magli; Riccardo Freddi; et al. (IGARSS, 2021)