An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction. - Alfio Di Mauro; Francesco Conti 001; Luca Benini (DAC, 2017)

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (PATMOS, 2017)

Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. - Antonio Pullini; Davide Rossi; Igor Loi; Alfio Di Mauro; Luca Benini (ESSCIRC, 2018)

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (ISCAS, 2018)

Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology. - Alfio Di Mauro; Florian Zaruba; Fabian Schuiki; Stefan Mach; Luca Benini (ISCAS, 2020)

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. - Hayate Okuhara; Ahmed Elnaqib; Davide Rossi; Alfio Di Mauro; Philipp Mayer; Pierpaolo Palestri; Luca Benini (ISCAS, 2020)

Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability. - Michael Hersche; Edoardo Mello Rella; Alfio Di Mauro; Luca Benini; Abbas Rahimi (ISLPED, 2020)

Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node. - Alfio Di Mauro; Francesco Conti 001; Pasquale Davide Schiavone; Davide Rossi; Luca Benini (CoRR, 2020)

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (CoRR, 2020)

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (Integr., 2020)

Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node. - Alfio Di Mauro; Francesco Conti 001; Pasquale Davide Schiavone; Davide Rossi; Luca Benini (IEEE Trans. Circuits Syst., 2020)

FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node. - Alfio Di Mauro; Moritz Scherer 001; Jordi Fornt Mas; Basile Bougenot; Michele Magno; Luca Benini (DATE, 2021)

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Angelo Garofalo; Gianmarco Ottavi; Alfio Di Mauro; Francesco Conti 001; Giuseppe Tagliavini; Luca Benini; Davide Rossi (ESSCIRC, 2021)

Towards Always-on Event-based Cameras for Long-lasting Battery-operated Smart Sensor Nodes. - Moritz Scherer 001; Philipp Mayer; Alfio Di Mauro; Michele Magno; Luca Benini (I2MTC, 2021)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. - Pasquale Davide Schiavone; Davide Rossi; Alfio Di Mauro; Frank K. Gürkaynak; Timothy Saxe; Mao Wang; Ket Chong Yap; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface. - Jiawei Liao; Lars Widmer; Xiaying Wang; Alfio Di Mauro; Samuel R. Nason-Tomaszewski; Cynthia A. Chestek; Luca Benini; Taekwang Jang (AICAS, 2022)

A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications. - Moritz Scherer 001; Alfio Di Mauro; Georg Rutishauser; Tim Fischer 001; Luca Benini (COOL CHIPS, 2022)

SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions. - Alfio Di Mauro; Arpan Suravi Prasad; Zhikai Huang; Matteo Spallanzani; Francesco Conti 001; Luca Benini (DATE, 2022)

Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs. - Alfio Di Mauro; Moritz Scherer 001; Davide Rossi; Luca Benini (HCS, 2022)

TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology. - Moritz Scherer 001; Alfio Di Mauro; Tim Fischer 001; Georg Rutishauser; Luca Benini (CoRR, 2022)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Embedded neuromorphic attention model leveraging a novel low-power heterogeneous platform. - Amélie Gruel; Alfio Di Mauro; Robin Hunziker; Luca Benini; Jean Martinet; Michele Magno (AICAS, 2023)

Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS. - Moritz Scherer 001; Manuel Eggimann; Alfio Di Mauro; Arpan Suravi Prasad; Francesco Conti 001; Davide Rossi; Jorge Tomás Gómez; Ziyun Li; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (ESSCIRC, 2023)

ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications. - Georg Rutishauser; Robin Hunziker; Alfio Di Mauro; Sizhen Bian; Luca Benini; Michele Magno (ISCAS, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

ColibriUAV: An Ultra-Fast, Energy-Efficient Neuromorphic Edge Processing UAV-Platform with Event-Based and Frame-Based Cameras. - Sizhen Bian; Lukas Schulthess; Georg Rutishauser; Alfio Di Mauro; Luca Benini; Michele Magno (IWASI, 2023)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (CoRR, 2023)

TCN-CUTIE: A 1, 036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology. - Moritz Scherer 001; Alfio Di Mauro; Tim Fischer 001; Georg Rutishauser; Luca Benini (IEEE Micro, 2023)

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Alfio Di Mauro; Luca Benini; Davide Rossi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Directly-trained Spiking Neural Networks for Deep Reinforcement Learning: Energy efficient implementation of event-based obstacle avoidance on a neuromorphic accelerator. - Luca Zanatta; Alfio Di Mauro; Francesco Barchi; Andrea Bartolini; Luca Benini; Andrea Acquaviva (Neurocomputing, 2023)

NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores. - Simone Manoni; Paul Scheffler; Alfio Di Mauro; Luca Zanatta; Andrea Acquaviva; Luca Benini; Andrea Bartolini (CF (Companion), 2024)

Circuits and Systems for Embodied AI: Exploring uJ Multi-Modal Perception for Nano-UAVs on the Kraken Shield. - Viviane Potocnik; Alfio Di Mauro; Lorenzo Lamberti; Victor Javier Kartsch; Moritz Scherer 001; Francesco Conti 001; Luca Benini (CoRR, 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. - Arpan Suravi Prasad; Moritz Scherer 001; Francesco Conti 001; Davide Rossi; Alfio Di Mauro; Manuel Eggimann; Jorge Tomás Gómez; Ziyun Li; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (IEEE J. Solid State Circuits, 2024)