On-Line Testable Logic Desgin for FPGA Implementation. - Alfred L. Burress; Parag K. Lala (ITC, 1997)

Self-Checking Logic Design for LUT-Based FPGAs. - Parag K. Lala; Alfred L. Burress (FPGA, 1999)

A technique for designing self-checking logic for FPGAs. - Parag K. Lala; Alfred L. Burress (ISCAS (1), 1999)

Self-checking logic design for FPGA implementation. - Parag K. Lala; Alfred L. Burress (IEEE Trans. Instrum. Meas., 2003)