A novel architecture for sine-output direct digital frequency synthesizers using parabolic approximation. - Amir M. Sodagar; G. Roientan Lahiji; Ali Azarpeyvand (ICECS, 2000)

Instruction reliability analysis for embedded processors. - Ali Azarpeyvand; Mostafa E. Salehi; Farshad Firouzi; Amir Yazdanbakhsh; Sied Mehdi Fakhraie (DDECS, 2010)

CIVA: Custom instruction vulnerability analysis framework. - Ali Azarpeyvand; Mostafa E. Salehi; Seid Mehdi Fakhraie (DDECS, 2012)

Vulnerability Analysis for Custom Instructions. - Ali Azarpeyvand; Mostafa E. Salehi; Sied Mehdi Fakhraie (DSD, 2012)

Adaptive fault-tolerant DVFS with dynamic online AVF prediction. - Farshad Firouzi; Ali Azarpeyvand; Mostafa E. Salehi; Sied Mehdi Fakhraie (Microelectron. Reliab., 2012)

Reliability-aware cross-layer custom instruction screening. - Bahareh J. Farahani; Ali Azarpeyvand; Saeed Safari; Seid Mehdi Fakhraie (DDECS, 2013)

An analytical method for reliability aware instruction set extension. - Ali Azarpeyvand; Mostafa E. Salehi; Sied Mehdi Fakhraie (J. Supercomput., 2014)

Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation. - Fatemeh Pouyan; Ali Azarpeyvand; Saeed Safari; Sied Mehdi Fakhraie (IET Comput. Digit. Tech., 2015)

An ultra-fast multi-objective optimization algorithm for VLIW architecture. - Samira Nazari; Maryam Hassani; Ali Azarpeyvand (EWDTS, 2016)

Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor. - Ali Azarpeyvand; Mostafa E. Salehi; Seid Mehdi Fakhraie; Saeed Safari (Microprocess. Microsystems, 2016)

Reliability aware throughput management of chip multi-processor architecture via thread migration. - Fatemeh Pouyan; Ali Azarpeyvand; Saeed Safari; Sied Mehdi Fakhraie (J. Supercomput., 2016)

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints. - Mostafa E. Salehi; Ali Azarpeyvand; Armin Hajaboutalebi Aboutalebi (J. Electron. Test., 2018)

Code Acceleration Using Memristor-Based Approximate Matrix Multiplier: Application to Convolutional Neural Networks. - Mohsen Nourazar; Vahid Rashtchi; Ali Azarpeyvand; Farshad Merrikh-Bayat (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Significantly improving human detection in low-resolution images by retraining YOLOv3. - Shima Pouyan; Mostafa Charmi; Ali Azarpeyvand; Hossein Hassanpoor (CSICC, 2021)

A Comprehensive Survey on Model Quantization for Deep Neural Networks. - Babak Rokh; Ali Azarpeyvand; Alireza Khanteymoori (CoRR, 2022)

Logarithm-approximate floating-point multiplier. - Samaneh Rezaei; Reza Omidi 001; Ali Azarpeyvand (Microelectron. J., 2022)

Data-Driven and Knowledge-Based Algorithms for Gene Network Reconstruction on High-Dimensional Data. - Omid Abbaszadeh; Ali Azarpeyvand; Alireza Khanteymoori; Abbas Bahari (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

Propounding First Artificial Intelligence Approach for Predicting Robbery Behavior Potential in an Indoor Security Camera. - Shima Pouyan; Mostafa Charmi; Ali Azarpeyvand; Hossein Hassanpoor (IEEE Access, 2023)

A Comprehensive Survey on Model Quantization for Deep Neural Networks in Image Classification. - Babak Rokh; Ali Azarpeyvand; Alireza Khanteymoori (ACM Trans. Intell. Syst. Technol., 2023)

PATROL: An Evolutionary APproach to Automatic Test Pattern Generation for Hardware TROjan Detection Leveraging PSO-GA Hybrid Techniques. - Mostafa Hosseini; Ali Azarpeyvand; Tara Ghasempouri (ATS, 2024)

FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs. - Samira Nazari; Mahdi Taheri; Ali Azarpeyvand; Mohsen Afsharchi; Tara Ghasempouri; Christian Herglotz; Masoud Daneshtalab; Maksim Jenihhin (ATS, 2024)

Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks. - Bahram Parchekani; Samira Nazari; Mohammad Hasan Ahmadilivani; Ali Azarpeyvand; Jaan Raik; Tara Ghasempouri; Masoud Daneshtalab (DFT, 2024)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. - Mahdi Taheri; Natalia Cherezova; Samira Nazari; Ahsan Rafiq; Ali Azarpeyvand; Tara Ghasempouri; Masoud Daneshtalab; Jaan Raik; Maksim Jenihhin (ETS, 2024)

Automatic High Functional Coverage Stimuli Generation for Assertion-based Verification. - Hossein Rostami; Mostafa Hosseini; Ali Azarpeyvand; Mohammad Reza Heidari Iman; Tara Ghasempouri (IOLTS, 2024)

Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation. - Saeed Sharifian Moghimi Moghaddam; Vahid Rashtchi; Ali Azarpeyvand (J. Supercomput., 2024)

Publisher Correction: Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation. - Saeed Sharifian Moghimi Moghaddam; Vahid Rashtchi; Ali Azarpeyvand (J. Supercomput., 2024)

A Double Approximate Neural Hardware Accelerator. - Samira Nazari; Ali Azarpeyvand; Tara Ghasempouri (CSICC, 2025)

SHIELD: PSO-Based Hardware Trojan Detection for Efficient and Low-Cost Defense. - Mostafa Hosseini; Ali Azarpeyvand; Mahdi Taheri; Tara Ghasempouri; Maksim Jenihhin (IOLTS, 2025)

SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions. - Ali Azarpeyvand; Mohammad Eslami; Gert Jervan; Jaan Raik; Tara Ghasempouri (ISVLSI, 2025)

Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization. - Samira Nazari; Mahdi Taheri; Ali Azarpeyvand; Mohsen Afsharchi; Christian Herglotz; Maksim Jenihhin (LATS, 2025)