Analyzing CUDA workloads using a detailed GPU simulator. - Ali Bakhoda; George L. Yuan; Wilson W. L. Fung; Henry Wong; Tor M. Aamodt (ISPASS, 2009)

Complexity effective memory access scheduling for many-core accelerator architectures. - George L. Yuan; Ali Bakhoda; Tor M. Aamodt (MICRO, 2009)

On-chip network design considerations for compute accelerators. - Ali Bakhoda; John Kim 001; Tor M. Aamodt (PACT, 2010)

Throughput-Effective On-Chip Networks for Manycore Accelerators. - Ali Bakhoda; John Kim 001; Tor M. Aamodt (MICRO, 2010)

Designing on-chip networks for throughput accelerators. - Ali Bakhoda; John Kim 001; Tor M. Aamodt (ACM Trans. Archit. Code Optim., 2013)

Bandwidth Bottleneck in Network-on-Chip for High-Throughput Processors. - Jiho Kim; Sanghun Cho; Minsoo Rhu; Ali Bakhoda; Tor M. Aamodt; John Kim 001 (PACT, 2020)

Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture. - Zhixian Jin; Christopher Rocca; Jiho Kim; Hans Kasan; Minsoo Rhu; Ali Bakhoda; Tor M. Aamodt; John Kim 001 (MICRO, 2024)