Impact of stress on various circuit characteristics in 65nm PDSOI technology. - Sushant Suryagandh; Mayank Gupta; Zhiyuan Wu; Srinath Krishnan; Mario Pelella; Jung-Suk Goo; Ciby Thuruthiyil; Judy X. An; Brian Q. Chen; Niraj Subba; Luis Zamudio; James Yonemura; et al. (ESSCIRC, 2007)

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. - Akif Sultan; John Faricelli; Sushant Suryagandh; Hans vanMeer; Kaveri Mathur; James Pattison; Sean Hannon; Greg Constant; Kalyana Kumar; Kevin Carrejo; Joe Meier; Rasit Onur Topaloglu; et al. (ISQED, 2009)

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables. - Bo Yu; Xin Li; James Yonemura; Zhiyuan Wu; Jung-Suk Goo; Ciby Thuruthiyil; Ali Icel (CICC, 2012)

Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications. - Sriram Balasubramanian; Ninad Pimparkar; Mangesh Kushare; Vinayak Mahajan; Juhi Bansal; Takashi Shimizu; Vivek Joshi; Kun Qian; Arunima Dasgupta; Karthik Chandrasekaran; Chad Weintraub; Ali Icel (ISQED, 2016)

Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection. - Pratik B. Vyas; Ninad Pimparkar; Robert Tu; Wafa Arfaoui; Germain Bossu; Mahesh Siddabathula; Steffen Lehmann; Jung-Suk Goo; Ali B. Icel (IRPS, 2021)