Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. - Mohammad K. Akbari; Ali Jahanian 001; Mohsen Naderi; Bahman Javadi (DSD, 2004)

Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. - Hamid Safizadeh; Hamid Noori; Mehdi Sedighi; Ali Jahanian 001; Neda Zolfaghari (DSD, 2005)

Prediction and reduction of routing congestion. - Mehdi Saeedi; Morteza Saheb Zamani; Ali Jahanian 001 (ISPD, 2006)

Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. - Ali Jahanian 001; Morteza Saheb Zamani (ISVLSI, 2006)

Improved timing closure by early buffer planning in floor-placement design flow. - Ali Jahanian 001; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2007)

Metro-on-chip: an efficient physical design technique for congestion reduction. - Ali Jahanian 001; Morteza Saheb Zamani (IEICE Electron. Express, 2007)

Evaluation, prediction and reduction of routing congestion. - Mehdi Saeedi; Morteza Saheb Zamani; Ali Jahanian 001 (Microelectron. J., 2007)

Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. - Ali Jahanian 001; Morteza Saheb Zamani; Mostafa Rezvani; Mehrdad Najibi (CSICC, 2008)

Performance and Timing Yield Enhancement using Highway-on-Chip Planning. - Ali Jahanian 001; Morteza Saheb Zamani (DSD, 2008)

Performance Improvement of Physical Retiming with Shortcut Insertion. - Adel Dokhanchi; Mostafa Rezvani; Ali Jahanian 001; Morteza Saheb Zamani (ISVLSI, 2008)

Using metro-on-chip in physical design flow for congestion and routability improvement. - Ali Jahanian 001; Morteza Saheb Zamani (Microelectron. J., 2008)

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. - Naser MohammadZadeh; Minoo Mirsaeedi; Ali Jahanian 001; Morteza Saheb Zamani (DATE, 2009)

Improved performance and yield with chip master planning design methodology. - Ali Jahanian 001; Morteza Saheb Zamani (ACM Great Lakes Symposium on VLSI, 2009)

A Landmark-Based Navigation System for High Speed Cars in the Roads with Branches. - Mercedeh Sanjabi; Somayeh Maabi; Zahra Esmaeili; Ali Jahanian 001; Sirvan Khalighi (Int. J. Inf. Acquis., 2009)

Early Buffer Planning with Congestion Control Using Buffer Requirement Map. - Ali Jahanian 001; Morteza Saheb Zamani (J. Circuits Syst. Comput., 2010)

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. - Behzad Salami 001; Morteza Saheb Zamani; Ali Jahanian 001 (DSD, 2011)

Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology. - Mehdi Alipour; Mohammad Haji Seyed Javadi; Ali Jahanian 001 (ACM Great Lakes Symposium on VLSI, 2011)

Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage. - Adel Dokhanchi; Ali Jahanian 001; Esfandiar Mehrshahi; Mohammad Taghi Teimoori (ISVLSI, 2011)

A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion. - Zohre Mohammadi-Arfa; Ali Jahanian 001 (ISVLSI, 2011)

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation. - Arash Farkish; Ali Jahanian 001 (IEICE Electron. Express, 2011)

Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. - Ali Jahanian 001; Morteza Saheb Zamani; Hamid Safizadeh (Integr., 2011)

RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion. - Bahareh Pourshirazi; Ali Jahanian 001 (DSD, 2012)

EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off. - Samaneh Talebi; Niloofar Abolghasemi; Ali Jahanian 001 (DSD, 2012)

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage. - Marzieh Morshedzadeh; Ali Jahanian 001 (ACM Great Lakes Symposium on VLSI, 2012)

Landmark-based Car Navigation with Overtake Capability in Multi-agent Environments. - Sirvan Khalighi; Somayeh Maabi; Mercedeh Sanjabi; Ali Jahanian 001 (ICAART (2), 2012)

Improved CMOS (4; 2) compressor designs for parallel multipliers. - Abdoreza Pishvaie; Ghassem Jaberipur; Ali Jahanian 001 (Comput. Electr. Eng., 2012)

Improved timing closure by analytical buffer and TSV planning in three-dimensional chips. - Reza Abdollahi; Ali Jahanian 001 (IEICE Electron. Express, 2012)

Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects. - Mohammad Taghi Teimoori; Ali Jahanian 001; Adel Dokhanchi (IEICE Trans. Electron., 2012)

Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. - Sharareh Zamanzadeh; Ali Jahanian 001 (VLSI-SoC, 2013)

Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware. - Mahmoud Bakhshizadeh; Ali Jahanian 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs. - Armin Belghadr; Ali Jahanian 001 (Integr., 2014)

Improved delay and Process variation Tolerant Clock Tree Network in ultra-Large Circuits using Hybrid RF/metal Clock Routing. - Zohre Mohammadi-Arfa; Ali Jahanian 001 (J. Circuits Syst. Comput., 2014)

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage. - Marzieh Morshedzadeh; Ali Jahanian 001; Payam Pourashraf (Integr., 2015)

Security-aware register placement to hinder malicious hardware updating and improve Trojan detectability. - Mehrshad Vosoughi; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2015)

A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform. - H. Daryanavard; Mohammad Eshghi; Ali Jahanian 001 (J. Supercomput., 2015)

Security improvement of FPGA configuration file against the reverse engineering attack. - Sharareh Zamanzadeh; Shahram Shahabi; Ali Jahanian 001 (ISCISC, 2016)

Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. - Sharareh Zamanzadeh; Ali Jahanian 001 (J. Electron. Test., 2016)

Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose. - Sharareh Zamanzadeh; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2016)

ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow. - Sharareh Zamanzadeh; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2016)

Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology. - Sharareh Zamanzadeh; Ali Jahanian 001 (Microprocess. Microsystems, 2016)

Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers. - Sharareh Zamanzadeh; Ali Jahanian 001 (AsianHOST, 2017)

High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation. - Mercedeh Sanjabi; Ali Jahanian 001; Maryam Tahmasebi (DSD, 2017)

Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution. - Hamed Hossein-Talaee; Ali Jahanian 001 (ISVLSI, 2017)

Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area. - Armin Belghadr; Ali Jahanian 001 (J. Circuits Syst. Comput., 2017)

Customized Placement Algorithm of Nanoscale DNA Logic Circuits. - Sedigheh Farhadtoosky; Ali Jahanian 001 (J. Circuits Syst. Comput., 2017)

DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design. - Zohre Mohammadi-Arfa; Ali Jahanian 001 (IEEE Trans. Biomed. Circuits Syst., 2017)

Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management. - Pourya Bayat-Makou; Ali Jahanian 001; Midia Reshadi (CCECE, 2018)

Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation. - Zohre Beiki; Z. Zare Dorabi; Ali Jahanian 001 (Microprocess. Microsystems, 2018)

Cost-Effective and Practical Countermeasure against the Template Side Channel Attack. - Farshideh Kordi; Hamed Hossein-Talaee; Ali Jahanian 001 (ISCISC, 2020)

Analysis of Geometrical Parameters for Remote Side-Channel Attacks on Multi-Tenant FPGAs. - Milad Salimian; Ali Jahanian 001 (ISCISC, 2020)

Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection. - Mahboube Fakhire; Ali Jahanian 001 (ISVLSI, 2020)

A Cost & Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip. - Alireza Abdoli; Ali Jahanian 001 (CoRR, 2020)

Low-Cost Performance-Efficient Field-Programmable Pin-Constrained Digital Microfluidic Biochip. - Alireza Abdoli; Sedigheh Farhadtoosky; Ali Jahanian 001 (CoRR, 2020)

Intensive Analysis of Physical Parameters of Power Sensors for Remote Side-Channel Attacks. - Milad Salimian; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2021)

Flexible and Automatable Microfluidic-based Architecture and CAD Algorithm for Implementation of Large DNA Digital Storage. - Mostafa Pourasadollah; Maryam Taajobian; Ali Jahanian 001 (CSICC, 2022)

A Time Randomization-Based Countermeasure Against the Template Side-Channel Attack. - Farshideh Kordi; Hamed Hossein-Talaee; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2022)

A Closed-Form Transient Response of Coupled Transmission Lines. - Fatemeh Zahedi; Esfandiar Mehrshahi; Ali Jahanian 001 (IEEE Syst. J., 2022)

Accurate Crosstalk Noise Modeling and Analysis of Non-Identical Lossy Interconnections Using Convex Optimization Method. - Fatemeh Zahedi; Esfandiar Mehrshahi; Ali Jahanian 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process. - Vahhab Samadi Bokharaie; Ali Jahanian 001 (J. Supercomput., 2022)

Generic and scalable DNA-based logic design methodology for massive parallel computation. - Zohre Beiki; Ali Jahanian 001 (J. Supercomput., 2023)

Systematic Trojan Detection in Crypto-Systems Using the Model Checker. - Hamed Hossein-Talaee; Ali Jahanian 001; Bijan Alizadeh (J. Circuits Syst. Comput., 2024)