Modeling Instruction-Level Parallelism for Software Pipelining. - Ali-Reza Adl-Tabatabai; Thomas R. Gross; Guei-Yuan Lueh; James Reinders (Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993)

Detection and Recovery of Endangered Variables Caused by Instruction Scheduling. - Ali-Reza Adl-Tabatabai; Thomas R. Gross (PLDI, 1993)

Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging. - Ali-Reza Adl-Tabatabai; Thomas R. Gross (POPL, 1993)

Global Register Allocation Based on Graph Fusion. - Guei-Yuan Lueh; Thomas R. Gross; Ali-Reza Adl-Tabatabai (LCPC, 1996)

Code Reuse in an Optimizing Compiler. - Ali-Reza Adl-Tabatabai; Thomas R. Gross; Guei-Yuan Lueh (OOPSLA, 1996)

Source-Level Debugging of Scalar Optimized Code. - Ali-Reza Adl-Tabatabai; Thomas R. Gross (PLDI, 1996)

Efficient and Language-Independent Mobile Programs. - Ali-Reza Adl-Tabatabai; Geoff Langdale; Steven Lucco; Robert Wahbe (PLDI, 1996)

Fast, Effective Code Generation in a Just-In-Time Java Compiler. - Ali-Reza Adl-Tabatabai; Michal Cierniak; Guei-Yuan Lueh; Vishesh M. Parikh; James M. Stichnoth (PLDI, 1998)

Fusion-based register allocation. - Guei-Yuan Lueh; Thomas R. Gross; Ali-Reza Adl-Tabatabai (ACM Trans. Program. Lang. Syst., 2000)

Just-In-Time Java? Compilation for the Itanium® Processor. - Tatiana Shpeisman; Guei-Yuan Lueh; Ali-Reza Adl-Tabatabai (IEEE PACT, 2002)

Improving 64-Bit Java IPF Performance by Compressing Heap References. - Ali-Reza Adl-Tabatabai; Jay Bharadwaj; Michal Cierniak; Marsha Eng; Jesse Fang; Brian T. Lewis; Brian R. Murphy; James M. Stichnoth (CGO, 2004)

Prefetch inection based on hardware monitoring and object metadata. - Ali-Reza Adl-Tabatabai; Richard L. Hudson; Mauricio J. Serrano; Sreenivas Subramoney (PLDI, 2004)

Transactional memory introduction. - Ali-Reza Adl-Tabatabai (Hot Chips Symposium, 2006)

McRT-Malloc: a scalable transactional memory allocator. - Richard L. Hudson; Bratin Saha; Ali-Reza Adl-Tabatabai; Ben Hertzberg (ISMM, 2006)

Architectural Support for Software Transactional Memory. - Bratin Saha; Ali-Reza Adl-Tabatabai; Quinn Jacobson (MICRO, 2006)

Compiler and runtime support for efficient software transactional memory. - Ali-Reza Adl-Tabatabai; Brian T. Lewis; Vijay Menon 002; Brian R. Murphy; Bratin Saha; Tatiana Shpeisman (PLDI, 2006)

A verifiable SSA program representation for aggressive compiler optimization. - Vijay Menon 002; Neal Glew; Brian R. Murphy; Andrew McCreight; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai; Leaf Petersen (POPL, 2006)

McRT-STM: a high performance software transactional memory system for a multi-core runtime. - Bratin Saha; Ali-Reza Adl-Tabatabai; Richard L. Hudson; Chi Cao Minh; Ben Hertzberg (PPoPP, 2006)

Unlocking concurrency. - Ali-Reza Adl-Tabatabai; Christos Kozyrakis; Bratin Saha (ACM Queue, 2006)

Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. - Cheng Wang 013; Wei-Yu Chen; Youfeng Wu; Bratin Saha; Ali-Reza Adl-Tabatabai (CGO, 2007)

Enabling scalability and performance in a large scale CMP environment. - Bratin Saha; Ali-Reza Adl-Tabatabai; Anwar M. Ghuloum; Mohan Rajagopalan; Richard L. Hudson; Leaf Petersen; Vijay Menon 002; Brian R. Murphy; Tatiana Shpeisman; Eric Sprangle; Anwar Rohillah; Doug Carmean; et al. (EuroSys, 2007)

Compression in cache design. - Ali-Reza Adl-Tabatabai; Anwar M. Ghuloum; Shobhit O. Kanaujia (ICS, 2007)

Enforcing isolation and ordering in STM. - Tatiana Shpeisman; Vijay Menon 002; Ali-Reza Adl-Tabatabai; Steven Balensiefer; Dan Grossman; Richard L. Hudson; Katherine F. Moore; Bratin Saha (PLDI, 2007)

Potential show-stoppers for transactional synchronization. - Ali-Reza Adl-Tabatabai; David Dice; Maurice Herlihy; Nir Shavit; Christos Kozyrakis; Christoph von Praun; Michael L. Scott (PPoPP, 2007)

Transactional programming in a multi-core environment. - Ali-Reza Adl-Tabatabai; Christos Kozyrakis; Bratin Saha (PPoPP, 2007)

Open nesting in software transactional memory. - Yang Ni; Vijay Menon 002; Ali-Reza Adl-Tabatabai; Antony L. Hosking; Richard L. Hudson; J. Eliot B. Moss; Bratin Saha; Tatiana Shpeisman (PPoPP, 2007)

Fault-safe code motion for type-safe languages. - Brian R. Murphy; Vijay Menon 002; Florian T. Schneider; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai (CGO, 2008)

A Uniform Transactional Execution Environment for Java. - Lukasz Ziarek; Adam Welc; Ali-Reza Adl-Tabatabai; Vijay Menon 002; Tatiana Shpeisman; Suresh Jagannathan (ECOOP, 2008)

Transactional memory: from semantics to silicon. - Ali-Reza Adl-Tabatabai (IWMSE@ICSE, 2008)

Design and implementation of transactional constructs for C/C++. - Yang Ni; Adam Welc; Ali-Reza Adl-Tabatabai; Moshe Bach; Sion Berkowits; James Cownie; Robert Geva; Sergey Kozhukow; Ravi Narayanaswamy; Jeffrey Olivier; Serguei Preis; Bratin Saha; et al. (OOPSLA, 2008)

Dynamic optimization for efficient strong atomicity. - Florian T. Schneider; Vijay Menon 002; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai (OOPSLA, 2008)

Concurrent GC leveraging transactional memory. - Phil McGachey; Ali-Reza Adl-Tabatabai; Richard L. Hudson; Vijay Menon 002; Bratin Saha; Tatiana Shpeisman (PPoPP, 2008)

Practical weak-atomicity semantics for java stm. - Vijay Menon 002; Steven Balensiefer; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai; Richard L. Hudson; Bratin Saha; Adam Welc (SPAA, 2008)

Irrevocable transactions and their applications. - Adam Welc; Bratin Saha; Ali-Reza Adl-Tabatabai (SPAA, 2008)

Kicking the tires of software transactional memory: why the going gets tough. - Richard M. Yoo; Yang Ni; Adam Welc; Bratin Saha; Ali-Reza Adl-Tabatabai; Hsien-Hsin S. Lee (SPAA, 2008)

Single global lock semantics in a weakly atomic STM. - Vijay Menon 002; Steven Balensiefer; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai; Richard L. Hudson; Bratin Saha; Adam Welc (ACM SIGPLAN Notices, 2008)

NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems. - Haris Volos 001; Adam Welc; Ali-Reza Adl-Tabatabai; Tatiana Shpeisman; Xinmin Tian; Ravi Narayanaswamy (ECOOP, 2009)

An analytic model of optimistic Software Transactional Memory. - Armin Heindl; Gilles Pokam; Ali-Reza Adl-Tabatabai (ISPASS, 2009)

Architecting a chunk-based memory race recorder in modern CMPs. - Gilles Pokam; Cristiano Pereira; Klaus Danne; Rolf Kassa; Ali-Reza Adl-Tabatabai (MICRO, 2009)

Optimizing transactions for captured memory. - Aleksandar Dragojevic; Yang Ni; Ali-Reza Adl-Tabatabai (SPAA, 2009)

Towards transactional memory semantics for C++. - Tatiana Shpeisman; Ali-Reza Adl-Tabatabai; Robert Geva; Yang Ni; Adam Welc (SPAA, 2009)

Optimizing Memory Transactions for Multicore Systems. - Ali-Reza Adl-Tabatabai; Christos Kozyrakis; Bratin Saha (Multicore Processors and Systems, 2009)

Generic workers: towards unified distributed and parallel JavaScript programming model. - Adam Welc; Richard L. Hudson; Tatiana Shpeisman; Ali-Reza Adl-Tabatabai (PSI EtA, 2010)

CoreRacer: a practical memory race recorder for multicore x86 TSO processors. - Gilles Pokam; Cristiano Pereira; Shiliang Hu; Ali-Reza Adl-Tabatabai; Justin Emile Gottschlich; Jungwoo Ha; Youfeng Wu (MICRO, 2011)

A study of transactional memory vs. locks in practice. - Victor Pankratius; Ali-Reza Adl-Tabatabai (SPAA, 2011)

Efficient Mapping of Irregular C++ Applications to Integrated GPUs. - Rajkishore Barik; Rashid Kaleem; Deepak Majeti; Brian T. Lewis; Tatiana Shpeisman; Chunling Hu; Yang Ni; Ali-Reza Adl-Tabatabai (CGO, 2014)

Software Engineering with Transactional Memory Versus Locks in Practice. - Victor Pankratius; Ali-Reza Adl-Tabatabai (Theory Comput. Syst., 2014)

Keeping Master Green at Scale. - Sundaram Ananthanarayanan; Masoud Saeida Ardekani; Denis Haenikel; Balaji Varadarajan; Simon Soriano; Dhaval Patel; Ali-Reza Adl-Tabatabai (EuroSys, 2019)