A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC. - Fan Zhang 049; Yanqing Zhang 002; Jason Silver; Yousef Shakhsheer; Manohar Nagaraju; Alicia Klinefelter; Jagdish Nayayan Pandey; James Boley; Eric J. Carlson; Aatmesh Shrivastava; Brian P. Otis; Benton H. Calhoun (ISSCC, 2012)

A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC. - Alicia Klinefelter; Yanqing Zhang 002; Brian P. Otis; Benton H. Calhoun (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications. - Yanqing Zhang 002; Fan Zhang 049; Yousef Shakhsheer; Jason Silver; Alicia Klinefelter; Manohar Nagaraju; James Boley; Jagdish Nayayan Pandey; Aatmesh Shrivastava; Eric J. Carlson; Austin Wood; Benton H. Calhoun; et al. (IEEE J. Solid State Circuits, 2013)

Error-energy analysis of hardware logarithmic approximation methods for low power applications. - Alicia Klinefelter; Joseph F. Ryan 002; James W. Tschanz; Benton H. Calhoun (ISCAS, 2015)

21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios. - Alicia Klinefelter; Nathan E. Roberts; Yousef Shakhsheer; Patricia González; Aatmesh Shrivastava; Abhishek Roy 002; Kyle Craig; Muhammad Faisal; James Boley; Seunghyun Oh; Yanqing Zhang 002; Divya Akella; et al. (ISSCC, 2015)

A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems. - Abhishek Roy 002; Alicia Klinefelter; Farah B. Yahya; Xing Chen 004; Luisa Patricia Gonzalez-Guerrero; Christopher J. Lukas; Divya Akella Kamakshi; James Boley; Kyle Craig; Muhammad Faisal; Seunghyun Oh; Nathan E. Roberts; et al. (IEEE Trans. Biomed. Circuits Syst., 2015)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. - Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Stephen G. Tell; Brian Zimmer; Tezaswi Raja; Kevin Zhou; William J. Dally; Brucek Khailany (ASYNC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Accelerating Chip Design With Machine Learning. - Brucek Khailany; Haoxing Ren; Steve Dai; Saad Godil; Ben Keller; Robert Kirby 001; Alicia Klinefelter; Rangharajan Venkatesan; Yanqing Zhang 002; Bryan Catanzaro; William J. Dally (IEEE Micro, 2020)

F4: Electronics for a Quantum World. - Edoardo Charbon; Alicia Klinefelter; Massimo Alioto; Yao-Hong Liu; Munehiko Nagatani; Arijit Raychowdhury; Andreia Cathelin; Boris Murmann (ISSCC, 2021)

SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. - Alicia Klinefelter; Huichu Liu; Luca Benini; Yvain Thonnart; Keith A. Bowman; Kathy Wilcox; David Bol; Alvin Loke; Ofer Shacham (ISSCC, 2021)

SE4: ICs in PandemICs. - Negar Reiskarimian; Zeynep Toprak Deniz; Ulkuhan Guler 001; Kathy Wilcox; Alice Wang; Jane Gu; Yaoyao Jia; Alicia Klinefelter; Rikky Muller; Farhana Sheikh; Yildiz Sinangil; Trudy Stetzler; et al. (ISSCC, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. - Steve Dai; Alicia Klinefelter; Haoxing Ren; Rangharajan Venkatesan; Ben Keller; Nathaniel Ross Pinckney; Brucek Khailany (CoRR, 2021)