A Method to Design Compact Dual-rail Asynchronous Primitives. - Alin Razafindraibe; Michel Robert; Marc Renaudin; Philippe Maurine (PATMOS, 2005)

Compact and Secured Primitives for the Design of Asynchronous Circuits. - Alin Razafindraibe; Michel Robert; Philippe Maurine (J. Low Power Electron., 2005)

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. - Alin Razafindraibe; Michel Robert; Philippe Maurine (PATMOS, 2006)

Security evaluation of dual rail logic against DPA attacks. - Alin Razafindraibe; Philippe Maurine; Michel Robert; Marc Renaudin (VLSI-SoC, 2006)

A Novel Asynchronous e-FPGA Architecture for Security Applications. - Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin; Sumanta Chaudhuri; Sylvain Guilley; Jean-Luc Danger; Philippe Hoogvorst (FPT, 2007)

A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. - Alin Razafindraibe; Philippe Maurine (PATMOS, 2007)

Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. - Alin Razafindraibe; Michel Robert; Philippe Maurine (PATMOS, 2007)

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Alin Razafindraibe; Taha Beyrouthy; Laurent Fesquet (ReCoSoC, 2007)

Improvement of dual rail logic as a countermeasure against DPA. - Alin Razafindraibe; Michel Robert; Philippe Maurine (VLSI-SoC, 2007)

Physical Design of FPGA Interconnect to Prevent Information Leakage. - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (ARC, 2008)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (CoRR, 2011)