Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. - Alireza Mahzoon; Bijan Alizadeh (ISVLSI, 2015)

Systematic Design Space Exploration of Floating-Point Expressions on FPGA. - Alireza Mahzoon; Bijan Alizadeh (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. - Alireza Mahzoon; Bijan Alizadeh (IEEE Trans. Very Large Scale Integr. Syst., 2017)

PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (ICCAD, 2018)

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (ISVLSI, 2018)

RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (DAC, 2019)

Towards Formal Verification of Optimized and Industrial Multipliers. - Alireza Mahzoon; Daniel Große; Christoph Scholl 001; Rolf Drechsler (DATE, 2020)

ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. - Mehran Goli; Alireza Mahzoon; Rolf Drechsler (ICCD, 2020)

Polynomial Formal Verification of Prefix Adders. - Alireza Mahzoon; Rolf Drechsler (ATS, 2021)

Late Breaking Results: Polynomial Formal Verification of Fast Adders. - Alireza Mahzoon; Rolf Drechsler (DAC, 2021)

Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. - Christoph Scholl 001; Alexander Konrad; Alireza Mahzoon; Daniel Große; Rolf Drechsler (DATE, 2021)

Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. - Mehran Goli; Alireza Mahzoon; Rolf Drechsler (DSD, 2021)

Polynomial word-level verification of arithmetic circuits. - Mohammed Barhoush; Alireza Mahzoon; Rolf Drechsler (MEMOCODE, 2021)

Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. - Alireza Mahzoon; Daniel Große; Christoph Scholl 001; Alexander Konrad; Rolf Drechsler (DAC, 2022)

Towards Polynomial Formal Verification of Complex Arithmetic Circuits. - Rolf Drechsler; Alireza Mahzoon; Mehran Goli (DDECS, 2022)

Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. - Alexander Konrad; Christoph Scholl 001; Alireza Mahzoon; Daniel Große; Rolf Drechsler (FMCAD, 2022)

Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. - Rolf Drechsler; Alireza Mahzoon (ICCAD, 2022)

Polynomial Formal Verification of Complex Multipliers. - Alireza Mahzoon; Rolf Drechsler (MBMV, 2022)

ANN-based Performance Estimation of Embedded Software for RISC-V Processors. - Weiyan Zhang; Mehran Goli; Alireza Mahzoon; Rolf Drechsler (RSP, 2022)

Preserving Design Hierarchy Information for Polynomial Formal Verification. - Rolf Drechsler; Alireza Mahzoon (VLSI-SoC, 2022)

RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. - Alireza Mahzoon; Daniel Große; Rolf Drechsler (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Formal verification of structurally complex multipliers. - Alireza Mahzoon (2022)

Formale Verifikation von strukturell komplexen Multiplizierern. - Alireza Mahzoon (Ausgezeichnete Informatikdissertationen, 2022)

Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. - Alireza Mahzoon; Rolf Drechsler (Applicable Formal Methods for Safe Industrial Products, 2023)

Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. - Rolf Drechsler; Alireza Mahzoon (DATE, 2023)

Polynomial Formal Verification of Floating Point Adders. - Jan Kleinekathöfer; Alireza Mahzoon; Rolf Drechsler (DATE, 2023)

Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. - Rolf Drechsler; Alireza Mahzoon (ISDCS, 2023)

Polynomial Formal Verification of a Processor: A RISC-V Case Study. - Lennart Weingarten; Alireza Mahzoon; Mehran Goli; Rolf Drechsler (ISQED, 2023)

Polynomial Formal Verification of Arithmetic Circuits. - Alireza Mahzoon; Rolf Drechsler (Found. Trends Electron. Des. Autom., 2024)

Lower bound proof for the size of BDDs representing a shifted addition. - Jan Kleinekathöfer; Alireza Mahzoon; Rolf Drechsler (Inf. Process. Lett., 2025)