A new algorithm for transistor sizing in CMOS circuits. - Allen C.-H. Wu; Nels Vander Zanden; Daniel Gajski (EURO-DAC, 1990)

Glue-logic partitioning for floorplans with a rectilinear datapath. - Allen C.-H. Wu; Daniel D. Gajski (EURO-DAC, 1991)

Layout-Area Models for High-Level Synthesis. - Allen C.-H. Wu; Viraphol Chaiyakul; Daniel Gajski (ICCAD, 1991)

Youn-Long Steve Lin - Daniel D. Gajski; Nikil D. Dutt; Allen C.-H. Wu (Springer, 1992)

Timing models for high-level synthesis. - Viraphol Chaiyakul; Allen C.-H. Wu; Daniel D. Gajski (EURO-DAC, 1992)

An effective methodology for functional pipelining. - Tsing-Fa Lee; Allen C.-H. Wu; Daniel Gajski; Youn-Long Lin (ICCAD, 1992)

Accurate layout area and delay modeling for system level design. - Champaka Ramachandran; Fadi J. Kurdahi; Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul (ICCAD, 1992)

An efficient multi-view design model for real-time interactive synthesis. - Allen C.-H. Wu; Tedd Hadley; Daniel Gajski (ICCAD, 1992)

Layout placement for sliced architecture. - Lawrence L. Larmore; Daniel D. Gajski; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Partitioning algorithms for layout synthesis from register-transfer netlists. - Allen C.-H. Wu; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Combining technology mapping and placement for delay-optimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCAD, 1993)

A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. - Tsung-Yi Wu; Tzu-Chieh Tien; Allen C.-H. Wu; Youn-Long Lin (EDAC-ETC-EUROASIC, 1994)

State Assignment for Power and Area Minimization. - Kuo-Hua Wang; Wen-Sing Wang; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCD, 1994)

A transformation-based method for loop folding. - Tsing-Fa Lee; Allen C.-H. Wu; Youn-Long Lin; Daniel D. Gajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

EMPAR: an interactive synthesis environment for hardware emulations. - Wen-Jong Fang; Allen C.-H. Wu; Tsing-Gen Lee (ASP-DAC, 1995)

High-Level Synthesis -A Tutorial. - Allen C.-H. Wu; Youn-Long Lin (IEICE Trans. Inf. Syst., 1995)

TRACER-fpga: a router for RAM-based FPGA's. - Ching-Dong Chen; Yuh-Sheng Lee; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Combining technology mapping and placement for delay-minimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. - Tsing-Gen Lee; Wen-Jong Fang; Allen C.-H. Wu (Softw. Pract. Exp., 1996)

DP-Gen: a datapath generator for multiple-FPGA applications. - Wen-Jong Fang; Allen C.-H. Wu; Ti-Yen Yen; Tsair-Chin Lin (ASP-DAC, 1997)

An entropy measure for power estimation of Boolean functions. - Chi-Hong Hwang; Allen C.-H. Wu (ASP-DAC, 1997)

Evaluating cost-performance tradeoffs for system level applications. - Wei-Liang Ing; Cheng-Tsung Hwang; Allen C.-H. Wu (ASP-DAC, 1997)

Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. - Wen-Jong Fang; Allen C.-H. Wu (DAC, 1997)

A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. - Wen-Jong Fang; Allen C.-H. Wu; Ti-Yen Yen (DAC, 1997)

Module Generation of Complex Macros for Logic-Emulation Applications. - Wen-Jong Fang; Allen C.-H. Wu; Duan-Ping Chen (FPGA, 1997)

Preserving HDL synthesis hierarchy for cell placement. - Yu-Wen Tsay; Wen-Jong Fang; Allen C.-H. Wu; Youn-Long Lin (ISPD, 1997)

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. - Wen-Jong Fang; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A performance and routability-driven router for FPGAs considering path delays. - Yuh-Sheng Lee; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Scheduling techniques for variable voltage low power designs. - Yann-Rue Lin; Cheng-Tsung Hwang; Allen C.-H. Wu (ACM Trans. Design Autom. Electr. Syst., 1997)

Datapath Optimization Using Layout Information: An Empirical Study. - Allen C.-H. Wu (VLSI Design, 1997)

Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. - Wen-Jong Fang; Allen C.-H. Wu (DAC, 1998)

Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (ISPD, 1998)

Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. - Wen-Jong Fang; Allen C.-H. Wu (IEEE Des. Test Comput., 1998)

A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. - Wen-Jong Fang; Peng-Cheng Kao; Allen C.-H. Wu (ASP-DAC, 1999)

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (DAC, 1999)

Module Generation of High Performance FPGA-Based Multipliers. - Kun-Ming Ho; Allen C.-H. Wu (FPGA, 1999)

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. - Hsiao-Pin Su; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

EmGen-a module generator for logic emulation applications. - Wen-Jong Fang; Allen C.-H. Wu; Duan-Ping Chen (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Embedded tutorial: essential issues for IP reuse. - Daniel Gajski; Allen C.-H. Wu; Viraphol Chaiyakul; Shojiro Mori; Tom Nukiyama; Pierre Bricaud (ASP-DAC, 2000)

Delay Budgeting for a Timing-Closure-Driven Design Method. - Chien-Chu Kuo; Allen C.-H. Wu (ICCAD, 2000)

Multiway FPGA partitioning by fully exploiting design hierarchy. - Wen-Jong Fang; Allen C.-H. Wu (ACM Trans. Design Autom. Electr. Syst., 2000)

A predictive system shutdown method for energy saving of event-driven computation. - Chi-Hong Hwang; Allen C.-H. Wu (ACM Trans. Design Autom. Electr. Syst., 2000)

Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). - Allen C.-H. Wu; Nikil D. Dutt (IEEE Trans. Very Large Scale Integr. Syst., 2000)

An RTL design-space exploration method for high-level applications. - Peng-Cheng Kao; Chih-Kuang Hsieh; Allen C.-H. Wu (ASP-DAC, 2001)

High-performance FIR generation based on a timing-driven architecture and component selection method. - Jerry C.-Y. Kao; C.-F. Su; Allen C.-H. Wu (ISCAS (4), 2002)

A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. - M.-J. Liao; C.-F. Su; Alex C.-Y. Chang; Allen C.-H. Wu (ISCAS (1), 2002)

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. - Alex C.-Y. Chang; Wu-An Kuo; Allen C.-H. Wu; TingTing Hwang (DATE, 2003)

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. - Jennifer Y.-L. Lo; Wu-An Kuo; Allen C.-H. Wu; TingTing Hwang (DATE, 2003)

Decomposition of Instruction Decoder for Low Power Design. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (DATE, 2004)

A fast lane and vehicle detection approach for autonomous vehicles. - Bing-Fei Wu; Chuan-Tsai Lin; Chao-Jung Chen; Tze-Chiuan Lai; Hsueh-Lung Liao; Allen C.-H. Wu (SIP, 2005)

Performance-driven crosstalk elimination at post-compiler level. - Wu-An Kuo; Yi-Ling Chiang; TingTing Hwang; Allen C.-H. Wu (ISCAS, 2006)

Decomposition of instruction decoders for low-power designs. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (ACM Trans. Design Autom. Electr. Syst., 2006)

A power-driven multiplication instruction-set design method for ASIPs. - Wu-An Kuo; TingTing Hwang; Allen C.-H. Wu (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. - Wu-An Kuo; Yi-Ling Chiang; TingTing Hwang; Allen C.-H. Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Elastylus: flexible haptic painting stylus. - Ruimin Lyu; Haojie Hao; Wei Chen; Yuan Liu 021; Feng Wang 001; Allen C.-H. Wu (SIGGRAPH Asia Emerging Technologies, 2015)

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (DATE, 2016)

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Crosstalk-aware TSV-buffer Insertion in 3D IC. - Yen-Hao Chen; Po-Chen Huang; Fu-Wei Chen; Allen C.-H. Wu; TingTing Hwang (SoCC, 2019)

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. - Pei-An Ho; Yen-Hao Chen; Allen C.-H. Wu; TingTing Hwang (SoCC, 2019)

A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. - Chin-Yu Sun; Allen C.-H. Wu; TingTing Hwang (CoRR, 2019)

A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). - Yen-Hao Chen; Allen C.-H. Wu; TingTing Hwang (ASP-DAC, 2021)

A novel privacy-preserving deep learning scheme without a cryptography component. - Chin-Yu Sun; Allen C.-H. Wu; TingTing Hwang (Comput. Electr. Eng., 2021)

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. - Cheng-Hsien Lin; Kuan-Ting Chen; Yi-Yu Liu; Allen C.-H. Wu; Tingting Hwang (ACM Trans. Design Autom. Electr. Syst., 2024)