Design of 5-level reduced switches count Η-bridge multilevel inverter. - Almachius Kahwa; Hidemine Obara; Yasutaka Fujimoto (AMC, 2018)

Estimation and Analysis of Power Loss in a Reduced Switches Count H-Bridge Multilevel Inverter. - Almachius Kahwa; Hidemine Obara; Yasutaka Fujimoto (ICM, 2019)

Analysis and Mitigation of Low-Order-Harmonic Neutral-Point Voltage and Current Ripples in Five-Level NPC-Based Inverters. - Almachius Kahwa; Hidemine Obara; Yasutaka Fujimoto (ISIE, 2023)

A Single-Carrier Modulation Strategy for the Reduction of the DC-Link Voltage Ripple of a 5-Level Multilevel DC-Link Inverter. - Almachius Kahwa; Besong John Ebot; Yasutaka Fujimoto; Francis Mwasilu; Joseph Olorunfemi Ojo (IECON, 2024)