An FPGA implementation architecture for decoding of polar codes. - Alptekin Pamuk (ISWCS, 2011)

A two phase successive cancellation decoder architecture for polar codes. - Alptekin Pamuk; Erdal Arikan (ISIT, 2013)

FPGA Implementation of Digital Channelizer. - Kadir Ayhan; Alptekin Pamuk; Bekir Ahmet Dogrusöz (SIU, 2022)