A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. - Alvin Leng Sun Loke; Robert K. Barnes; Tin Tin Wee; Michael M. Oshima; Charles E. Moore; Ronald R. Kennedy; Jim O. Barnes; Robert A. Zimmer; Kari L. Arave; H. Herman M. Pang; Tom E. Cynkar; Aaron M. Volz; et al. (CICC, 2005)

A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. - Alvin Leng Sun Loke; Robert K. Barnes; Tin Tin Wee; Michael M. Oshima; Charles E. Moore; Ronald R. Kennedy; Michael J. Gilsdorf (IEEE J. Solid State Circuits, 2006)

Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Michael M. Oshima; Wade L. Williams; Robert G. Lewis; Charles Lin Wang; Audie Hanpachern; Karen M. Tucker; Prashanth Gurunath; Gladney C. Asada; Chad O. Lackey; Tin Tin Wee; et al. (CICC, 2009)

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. - Dennis Michael Fischette; Alvin Leng Sun Loke; Michael M. Oshima; Bruce Andrew Doyle; Roland Bakalski; Richard Joseph DeSantis; Anand Thiruvengadam; Charles Lin Wang; Gerry R. Talbot; Emerson S. Fang (ISSCC, 2010)

An Embedded All-Digital Circuit to Measure PLL Response. - Dennis Michael Fischette; Alvin Leng Sun Loke; Richard Joseph DeSantis; Gerry R. Talbot (IEEE J. Solid State Circuits, 2010)

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. - Bruce Andrew Doyle; Alvin Leng Sun Loke; Sanjeev K. Maheshwari; Charles Lin Wang; Dennis Michael Fischette; Jeffrey G. Cooper; Sanjeev K. Aggarwal; Tin Tin Wee; Chad O. Lackey; Harishkumar S. Kedarnath; Michael M. Oshima; Gerry R. Talbot; et al. (A-SSCC, 2011)

Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference. - Hasnain Lakdawala; Alvin Leng Sun Loke (IEEE J. Solid State Circuits, 2012)

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Sanjeev K. Maheshwari; Dennis Michael Fischette; Charles Lin Wang; Tin Tin Wee; Emerson S. Fang (IEEE J. Solid State Circuits, 2012)

Nanoscale CMOS Implications on Analog/Mixed-Signal Design. - Alvin Leng Sun Loke; C. K. Lee; Burton Mike Leary (CICC, 2019)

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. - Alvin Leng Sun Loke; Da Yang 007; Tin Tin Wee; Jonathan L. Holland; Patrick Isakanian; Kern Rim; Sam Yang; Jacob S. Schneider; Giri Nallapati; Sreeker Dundigal; Hasnain Lakdawala; Behnam Amelifard; et al. (CICC, 2019)

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. - Wei-Chih Chen; Chin-Hua Wen; Chin-Ming Fu; Tsung-Hsien Tsai; Yu-Chi Chen; Wen-Hung Huang; Chien-Chun Tsai; Alvin Leng Sun Loke; C. H. Kenny (VLSI Circuits, 2020)

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. - Mao-Hsuan Chou; Ya-Tin Chang; Tsung-Hsien Tsai; Tsung-Che Lu; Chia-Chun Liao; Hung-Yi Kuo; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny C.-H. Hsieh; Alvin Leng Sun Loke; Mark Chen 001 (VLSI Circuits, 2020)

Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. - Saurabh Goyal; Sanjay Kumar Wadhwa; Divya Tripathi; Gaurav Agrawal; Krishna Thakur; Deependra Kumar Jain; Alvin Leng Sun Loke; Atul Kumar; Manish Kumar Upadhyay; Bhawna; Sanjoy Kumar Dey (VLSID, 2023)