Fourier Transform Computers Using CORDIC Iterations. - Alvin M. Despain (IEEE Trans. Computers, 1974)

Communication In X-TREE, A Modular Multiprocessor System. - Carlo H. Séquin; Alvin M. Despain; David A. Patterson 001 (ACM Annual Conference (1), 1978)

X-Tree: A Tree Structured Multi-Processor Computer Architecture. - Alvin M. Despain; David A. Patterson 001 (ISCA, 1978)

Very Fast Fourier Transform Algorithms Hardware for Implementation. - Alvin M. Despain (IEEE Trans. Computers, 1979)

The Aquarius Project. - Alvin M. Despain; Yale N. Patt (COMPCON, 1984)

Design decisions influencing the microarchitecture for a Prolog machine. - Tep P. Dobry; Yale N. Patt; Alvin M. Despain (MICRO, 1984)

Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations. - Erling Wold; Alvin M. Despain (IEEE Trans. Computers, 1984)

AND-Parallelism of Logic Programs Based on a Static Data Dependency Analysis. - Jung-Herng Chang; Alvin M. Despain; Doug DeGroot (COMPCON, 1985)

Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. - Alvin M. Despain; Yale N. Patt (COMPCON, 1985)

Performance Studies of a Prolog Machine Architecture. - Tep P. Dobry; Alvin M. Despain; Yale N. Patt (ISCA, 1985)

Compiling Prolog into microcode: a case study using the NCR/32-000. - Barry S. Fagin; Yale N. Patt; Vason P. Srini; Alvin M. Despain (MICRO, 1985)

Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency Analysis. - Jung-Herng Chang; Alvin M. Despain (SLP, 1985)

Fast fourier transform processors using Gaussian residue arithmetic. - Alvin M. Despain; Allen M. Peterson; Oscar S. Rothaus; Erling Wold (J. Parallel Distributed Comput., 1985)

High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. - Alvin M. Despain; Yale N. Patt; Tep P. Dobry; Jung-Herng Chang; Wayne Citrin (COMPCON, 1986)

Delay reduction using simulated annealing. - Jonathan D. Pincus; Alvin M. Despain (DAC, 1986)

Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. - Philip Bitar; Alvin M. Despain (ISCA, 1986)

Performance Studies of a Parallel Prolog Architecture. - Barry S. Fagin; Alvin M. Despain (ISCA, 1987)

Experience with Prolog as a Hardware Specification Language. - William R. Bush; Gino Cheng; Patrick C. McGeer; Alvin M. Despain (SLP, 1987)

An Empirical Study of the Warren Abstract Machine. - Hervé J. Touati; Alvin M. Despain (SLP, 1987)

Aquarius. - Alvin M. Despain; Yale N. Patt; Vason P. Srini; Philip Bitar; William R. Bush; C. Chien; Wayne Citrin; Barry Fagin; Wenwei Hwu; Stephen W. Melvin; Rick McGeer; Ashok Singhal; et al. (SIGARCH Comput. Archit. News, 1987)

Prolog at Berkeley. - Alvin M. Despain (COMPCON, 1988)

A two-tier memory architecture for high-performance multiprocessor systems. - Tam M. Nguyen; Vason P. Srini; Alvin M. Despain (ICS, 1988)

The Aquarius IIU System. - Darren R. Busing; Vason P. Srini; Georges E. Smine; Michael J. Carlton; Alvin M. Despain (ICSI, 1990)

Fast Prolog with an Extended General Purpose Architecture. - Bruce K. Holmer; Barton Sano; Michael J. Carlton; Peter Van Roy; Ralph Clarke Haygood; William R. Bush; Alvin M. Despain; Joan M. Pendleton; Tep P. Dobry (ISCA, 1990)

The Benefits of Global Dataflow Analysis for an Optimizing Prolog Compiler. - Peter Van Roy; Alvin M. Despain (NACLP, 1990)

Scalable Shared-Memory Multiprocessor Architectures. - Shreekant S. Thakkar; Michel Dubois 001; Anthony T. Laundrie; Gurindar S. Sohi; David V. James; Stein Gjessing; Manu Thapar; Bruce Delagi; Michael J. Carlton; Alvin M. Despain (Computer, 1990)

The Performance of Parallel Prolog Programs. - Barry S. Fagin; Alvin M. Despain (IEEE Trans. Computers, 1990)

AI and Design. - Saul Amarel; Alvin M. Despain; H. Penny Nii; Louis I. Steinberg; Marty Tenenbaum; Peter M. Will (IJCAI, 1991)

Viewing Instruction Set Design as an Optimization Problem. - Bruce K. Holmer; Alvin M. Despain (MICRO, 1991)

An integrated prolog architecture for symbolic and numeric executions. - Alvin M. Despain; Robert Yung (Ann. Math. Artif. Intell., 1991)

High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. - Ing-Jer Huang; Alvin M. Despain (DAC, 1992)

Application-Driven Design Automation for Microprocessor Design. - Iksoo Pyo; Ching-Long Su; Ing-Jer Huang; Kuo-Rueih Pan; Yong-Seon Koh; Chi-Ying Tsui; Hsu-Tsun Chen; Gino Cheng; Shihming Liu; Shiqun Wu; Alvin M. Despain (DAC, 1992)

High-Performance Logic Programming with the Aquarius Prolog Compiler. - Peter Van Roy; Alvin M. Despain (Computer, 1992)

Technology Decomposition and Mapping Targeting Low Power Dissipation. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (DAC, 1993)

PDAS: Processor design automation system. - Iksoo Pyo; Alvin M. Despain (EURO-DAC, 1993)

Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. - Ing-Jer Huang; Alvin M. Despain (ICCAD, 1993)

Efficient estimation of dynamic power consumption under a real delay model. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (ICCAD, 1993)

An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. - Ing-Jer Huang; Alvin M. Despain (MICRO, 1993)

The 16-fold way: a microparallel taxonomy. - Barton Sano; Alvin M. Despain (MICRO, 1993)

Prophetic branches: a branch architecture for code compaction and efficient execution. - Apoorv Srivastava; Alvin M. Despain (MICRO, 1993)

Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. - Ching-Long Su; Chi-Ying Tsui; Alvin M. Despain (COMPCON, 1994)

Hardware-software co-designing benchmark-driven superpipelined instruction set processors. - Ching-Long Su; Alvin M. Despain (COMPSAC, 1994)

Synthesis of Instruction Sets for Pipelined Microprocessors. - Ing-Jer Huang; Alvin M. Despain (DAC, 1994)

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (DAC, 1994)

Generating instruction sets and microarchitectures from applications. - Ing-Jer Huang; Alvin M. Despain (ICCAD, 1994)

Low power state assignment targeting two-and multi-level logic implementations. - Chi-Ying Tsui; Massoud Pedram; Chih-Ang Chen; Alvin M. Despain (ICCAD, 1994)

A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors. - Ching-Long Su; Chin-Chi Teng; Alvin M. Despain (ICPADS, 1994)

Branch with Masked Squashing in Superpipelined Processors. - Ching-Long Su; Alvin M. Despain (ISCA, 1994)

Minimizing branch misprediction penalties for superpipelined processors. - Ching-Long Su; Alvin M. Despain (MICRO, 1994)

Saving Power in the Control Path of Embedded Processors. - Ching-Long Su; Chi-Ying Tsui; Alvin M. Despain (IEEE Des. Test Comput., 1994)

Power efficient technology decomposition and mapping under an extended power consumption model. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A Fast State Assignment Procedure for Large FSMs. - Shihming Liu; Massoud Pedram; Alvin M. Despain (DAC, 1995)

Cache designs for energy efficiency. - Ching-Long Su; Alvin M. Despain (HICSS (1), 1995)

PLATO P: PLA Timing Optimization by Partitioning. - Shihming Liu; Massoud Pedram; Alvin M. Despain (ISCAS, 1995)

190-MHz CMOS 4-Kbyte Pipelined Caches. - Apoorv Srivastava; Yong-Seon Koh; Barton Sano; Alvin M. Despain (ISCAS, 1995)

Cache design trade-offs for power and performance optimization: a case study. - Ching-Long Su; Alvin M. Despain (ISLPD, 1995)

Synthesis of application specific instruction sets. - Ing-Jer Huang; Alvin M. Despain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Power estimation methods for sequential logic circuits. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Design and Analysis of Hardware for High-Performance Prolog. - Bruce K. Holmer; Barton Sano; Michael J. Carlton; Peter Van Roy; Alvin M. Despain (J. Log. Program., 1996)

Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. - Chi-Ying Tsui; José Monteiro 001; Massoud Pedram; Srinivas Devadas; Alvin M. Despain; Bill Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 1996)

State assignment based on two-dimensional placement and hypercube mapping. - Shihming Liu; Massoud Pedram; Alvin M. Despain (Integr., 1997)

Design and Simulation of the Aquarius-II Multiprocessor. - Vason P. Srini; Tam M. Nguyen; Darren R. Busing; Michael J. Carlton; Bruce K. Holmer; Georges E. Smine; Alvin M. Despain (J. Syst. Integr., 1997)

Simulating the Effect of Decoherence and Inaccuracies on a Quantum Computer. - Kevin M. Obenland; Alvin M. Despain (QCQC, 1998)

Low-power state assignment targeting two- and multilevel logic implementations. - Chi-Ying Tsui; Massoud Pedram; Alvin M. Despain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Position error signal estimation at high sampling rates using data and servo sector measurements. - Petros A. loannou; Elias B. Kosmatopoulos; Alvin M. Despain (CDC, 2002)

HiDISC: A Decoupled Architecture for Data-Intensive Application. - Won Woo Ro; Jean-Luc Gaudiot; Stephen P. Crago; Alvin M. Despain (IPDPS, 2003)

Position error signal estimation at high sampling rates using data and servo sector measurements. - Petros A. Ioannou; Elias B. Kosmatopoulos; Alvin M. Despain (IEEE Trans. Control. Syst. Technol., 2003)

Design and evaluation of a hierarchical decoupled architecture. - Won Woo Ro; Stephen P. Crago; Alvin M. Despain; Jean-Luc Gaudiot (J. Supercomput., 2006)