RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. - Akshay Sarman; Alwin Shaju; Rose George Kunthara; K. Neethu; Rekha K. James; John Jose (VLSI-SoC, 2022)

Hardware-Efficient ECC Processor Design using Non-Homogeneous Split Hybrid Karatsuba Multiplier. - Pruthvi Parate; Alwin Shaju; Sanampudi Gopala Krishna Reddy; D. R. Vasanthi; Madhav Rao (ISVLSI, 2024)

Non-Homogeneous Composite Karatsuba Multipliers Factored Hardware-Efficient ECDSA Generation and Verification Accelerator Units. - Pruthvi Parate; Alwin Shaju; Sanampudi Gopala Krishna Reddy; D. R. Vasanthi; Madhav Rao (ISQED, 2025)

Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation. - Pruthvi Parate; Alwin Shaju; D. R. Vasanthi; Madhav Rao (ISQED, 2025)

Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware Accelerators. - Pruthvi Parate; Daksh Sharma; Alwin Shaju; Madhav Rao (ISVLSI, 2025)