A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS. - Fulvio Spagna; Lidong Chen; Mamatha Deshpande; Yongping Fan; Doug Gambetta; Sujatha Gowder; Sitaraman Iyer; Rohit Kumar; Peter Kwok; Renuka Krishnamurthy; Chien-chun Lin; Ravindran Mohanavelu; et al. (ISSCC, 2010)

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. - Sudeep Puligundla; Fulvio Spagna; Lidong Chen; Amanda Tran (ITC, 2010)

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. - Shenggao Li; Fulvio Spagna; Ji Chen; Xiaoqing Wang; Luke Tong; Sujatha Gowder; Wenyan Jia; Roan Nicholson; Sitaraman Iyer; Rui Song; Lily Li; Meng-hung Chen; et al. (A-SSCC, 2018)

A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology. - Dong-Myung Choi; Yikui Dong; Roan Nicholson; Frank Liu 008; Wenyan Jia; Vadim Levin; Mike He; Sameer Pradhan; Jieqiong Du; Michael De Vita; Amanda Tran; Reza Navid; et al. (VLSI Technology and Circuits, 2024)