A low power low latency comparator for ramp ADC in CMOS imagers. - Amandeep Kaur 005; Mukul Sarkar (ISCAS, 2016)

A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs. - Abhishek Shrivastava; Amandeep Kaur 005; Mukul Sarkar (ISOCC, 2017)

An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors. - Amandeep Kaur 005; Deepak Mishra 003; Mukul Sarkar (IEEE SENSORS, 2018)

A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors. - Amandeep Kaur 005; Deepak Mishra 003; Mukul Sarkar (ISCAS, 2018)

A reconfigurable cyclic ADC for biomedical applications. - Amandeep Kaur 005; Deepak Mishra 003 (BioCAS, 2019)

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC. - Amandeep Kaur 005; Deepak Mishra 003; Mukul Sarkar (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A CMOS Image Sensor with Column-Parallel Cyclic-SAR ADC. - Amandeep Kaur 005; M. B. Karthik; Mukul Sarkar (ISCAS, 2020)

On-chip Pixel Reconstruction using Simple CNN for Sparsely Read CMOS Image Sensor. - Wilfred Kisku; Amandeep Kaur 005; Deepak Mishra 003 (AICAS, 2021)

A High Speed, Low Energy Comparator Based on Current Recycling Approach. - Bibhudutta Satapathy; Amandeep Kaur 005 (ISCAS, 2021)

CMOS image sensor with adaptive readout scheme for low power applications. - Varun Kumar; Bibhudatta Satapathy; Wilfred Kisku; Amandeep Kaur 005; Deepak Mishra 003 (MWSCAS, 2021)

A low kickback noise and low power dynamic comparator. - Bibhudutta Satapathy; Amandeep Kaur 005 (MWSCAS, 2021)

On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients. - Amandeep Kaur 005; Deepak Mishra 003; K. M. Amogh; Mukul Sarkar (IEEE Trans. Circuits Syst. Video Technol., 2021)

AI driven Wide Dynamic Range CMOS Image Sensor. - Wilfred Kisku; Mohit Bhushan; Amandeep Kaur 005; Deepak Mishra 003 (AICAS, 2022)

An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors. - Amandeep Kaur 005; Mukul Sarkar (ISCAS, 2022)

A Multiplying Digital to Analog Converter Insensitive to Component Mismatch. - Amandeep Kaur 005 (ISCAS, 2022)

An Intelligent CMOS Image Sensor System Using Edge Information for Image Classification. - Wilfred Kisku; Prateek Khandelwal; Amandeep Kaur 005; Deepak Mishra 003 (APCCAS, 2023)

On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention Mechanism. - Sandeep Kodam; Wilfred Kisku; Amandeep Kaur 005; Deepak Mishra 003 (APCCAS, 2023)

A Single Capacitor-Based Offset Reduction Technique for Energy-Efficient Dynamic Comparators. - Bibhudutta Satapathy; Amandeep Kaur 005 (ISCAS, 2023)

An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications. - Bibhudutta Satapathy; Amandeep Kaur 005 (Circuits Syst. Signal Process., 2023)

Efficient Framework with Sparse Acquisition in CMOS Image Sensors for Low-Power Edge Devices. - Wilfred Kisku; Amandeep Kaur 005; Deepak Mishra 003 (iSES, 2024)

A Dynamic Offset Reduction Technique to Mitigate the Effect of Threshold Mismatch in Energy Efficient Comparators. - Bibhudutta Satapathy; Amandeep Kaur 005 (IEEE Access, 2024)

An Intelligent System With Reduced Readout Power and Lightweight CNN for Vision Applications. - Wilfred Kisku; Amandeep Kaur 005; Deepak Mishra 003 (IEEE Trans. Circuits Syst. Video Technol., 2024)

ViT Coupled Efficient CMOS Image Sensor with Sparse Acquisition and Patch Selection. - Wilfred Kisku; Azad Singh; Amandeep Kaur 005; Deepak Mishra 003 (ISCAS, 2025)

An Asymmetric Static Comparator for RC Oscillator Achieving $21.6 text{ppm} /{}^{ circ} mathrm{C}$ Temperature-Stability. - Bibhudutta Satapathy; Dhananjay Harish Bhalwala; Amandeep Kaur 005 (NewCAS, 2025)

An Asymmetric Dynamic Comparator for Low-Offset, Low-Noise, and High-Speed Applications. - Bibhudutta Satpathy; Utkarsh Srivastava; Amandeep Kaur 005 (IEEE Trans. Instrum. Meas., 2025)

A Multiply-by-Two Switched-Capacitor Amplifier with Reduced Sensitivity to Capacitive Mismatch. - Bibhudutta Satapathy; Sivaiah Naali; Amandeep Kaur 005 (Circuits Syst. Signal Process., 2025)

An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing. - Bibhudutta Satapathy; Karan Jadhav; Amandeep Kaur 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)