Generic Architecture Platform for Multiprocessor System-On-Chip Design. - Amer Baghdadi; Nacer-Eddine Zergainoh; Damien Lyonnard; Ahmed Amine Jerraya (DIPES, 2000)

Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ludovic Tambour; Damien Lyonnard; Lovic Gauthier; Ahmed Amine Jerraya (DIPES, 2000)

Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; T. Roudier; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2000)

A generic wrapper architecture for multi-processor SoC cosimulation and design. - Sungjoo Yoo; Gabriela Nicolescu; Damien Lyonnard; Amer Baghdadi; Ahmed Amine Jerraya (CODES, 2001)

Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. - Damien Lyonnard; Sungjoo Yoo; Amer Baghdadi; Ahmed Amine Jerraya (DAC, 2001)

An efficient architecture model for systematic design of application-specific multiprocessor SoC. - Amer Baghdadi; Damien Lyonnard; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (DATE, 2001)

Component-based design approach for multicore SoCs. - Wander O. Cesário; Amer Baghdadi; Lovic Gauthier; Damien Lyonnard; Gabriela Nicolescu; Yanick Paviot; Sungjoo Yoo; Ahmed Amine Jerraya; Mario Diaz-Nava (DAC, 2002)

Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; Ahmed Amine Jerraya (IEEE Trans. Software Eng., 2002)

Exploration de l'espace des solutions architecturales dans le codesign. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; Ahmed Amine Jerraya (Tech. Sci. Informatiques, 2002)

Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. (Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC). - Amer Baghdadi (2002)

Embedded Application Prototyping on a Communication-Restricted Reconfigurable. - Arif Sasongko; Amer Baghdadi; Frédéric Rousseau 001; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2003)

Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform. - Arif Sasongko; Amer Baghdadi; Frédéric Rousseau 001; Ahmed Amine Jerraya (Des. Autom. Embed. Syst., 2003)

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. - Sang-Il Han; Amer Baghdadi; Marius Bonaciu; Soo-Ik Chae; Ahmed Amine Jerraya (DAC, 2004)

An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. - Ferid Gharsalli; Amer Baghdadi; Marius Bonaciu; Giedrius Majauskas; Wander O. Cesário; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2004)

A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ahmed Amine Jerraya (Ann. des Télécommunications, 2004)

Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ahmed Amine Jerraya (Int. J. Embed. Syst., 2005)

ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (DATE, 2006)

On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (GLOBECOM, 2006)

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. - Hazem Moussa; Olivier Muller; Amer Baghdadi; Michel Jézéquel (DATE, 2007)

Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. - Hazem Moussa; Amer Baghdadi; Michel Jézéquel (DAC, 2008)

Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. - Hazem Moussa; Amer Baghdadi; Michel Jézéquel (ISCAS, 2008)

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (IEEE International Workshop on Rapid System Prototyping, 2008)

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. - Atif Raza Jafri; Daoud Karakolah; Amer Baghdadi; Michel Jézéquel (DATE, 2009)

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. - Fabrizio Vacca; Guido Masera; Hazem Moussa; Amer Baghdadi; Michel Jézéquel (DSD, 2009)

High-Level System Modeling for Rapid HW/SW Architecture Exploration. - Chafic Jaber; Andreas Kanstein; Ludovic Apvrille; Amer Baghdadi; Patricia Le Moenner; Renaud Pacalet (IEEE International Workshop on Rapid System Prototyping, 2009)

Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. - Atif Raza Jafri; Amer Baghdadi; Michel Jézéquel (IEEE International Workshop on Rapid System Prototyping, 2009)

FPGA-based Radar Signal Processing for Automotive Driver Assistance System. - Jean Saad; Amer Baghdadi; Frantz Bodereau (IEEE International Workshop on Rapid System Prototyping, 2009)

ASIP-Based Universal Demapper for Multiwireless Standards. - Atif Raza Jafri; Amer Baghdadi; Michel Jézéquel (IEEE Embed. Syst. Lett., 2009)

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Rapid design and prototyping of universal soft demapper. - Atif Raza Jafri; Amer Baghdadi; Michel Jézéquel (ISCAS, 2010)

Power consumption analysis and energy efficient optimization for turbo decoder implementation. - Pallavi Reddy; Fabien Clermidy; Rasheed Al Khayat; Amer Baghdadi; Michel Jézéquel (SoC, 2010)

Parallelism Efficiency in Convolutional Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (EURASIP J. Adv. Signal Process., 2010)

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. - Purushotham Murugappa; Rachid Al-Khayat; Amer Baghdadi; Michel Jézéquel (DATE, 2011)

A low complexity stopping criterion for reducing power consumption in turbo decoders. - Pallavi Reddy; Fabien Clermidy; Amer Baghdadi; Michel Jézéquel (DATE, 2011)

Area and throughput optimized ASIP for multi-standard turbo decoding. - Rachid Al-Khayat; Purushotham Murugappa; Amer Baghdadi; Michel Jézéquel (International Symposium on Rapid System Prototyping, 2011)

Reducing the number of iterations in iterative demodulation with turbo decoding. - Salim Haddad; Amer Baghdadi; Michel Jézéquel (SoftCOM, 2011)

Parallel MIMO Turbo Equalization. - Atif Raza Jafri; Amer Baghdadi; Michel Jézéquel (IEEE Commun. Lett., 2011)

On chip interconnects for multiprocessor turbo decoding architectures. - Maurizio Martina; Guido Masera; Hazem Moussa; Amer Baghdadi (Microprocess. Microsystems, 2011)

Complexity reduction of shuffled parallel iterative demodulation with turbo decoding. - Salim Haddad; Oscar Sanchez; Amer Baghdadi; Michel Jézéquel (ICT, 2012)

Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm2 multi-standard turbo decoder. - Rachid Al-Khayat; Amer Baghdadi; Michel Jézéquel (ISSoC, 2012)

Adaptive complexity MIMO turbo receiver applying turbo demodulation. - Salim Haddad; Amer Baghdadi; Michel Jézéquel (ISTC, 2012)

An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. - Vianney Lapotre; Guy Gogniat; Jean-Philippe Diguet; Salim Haddad; Amer Baghdadi (ReConFig, 2012)

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. - Purushotham Murugappa; Jean-Noel Bazin; Amer Baghdadi; Michel Jézéquel (RSP, 2012)

Complexity adaptive iterative receiver performing TBICM-ID-SSD. - Salim Haddad; Amer Baghdadi; Michel Jézéquel (EURASIP J. Adv. Signal Process., 2012)

On the Convergence Speed of Turbo Demodulation With Turbo Decoding. - Salim Haddad; Amer Baghdadi; Michel Jézéquel (IEEE Trans. Signal Process., 2012)

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. - Guido Masera; Amer Baghdadi; Frank Kienle; Christophe Moy (VLSI Design, 2012)

Parameterized area-efficient multi-standard turbo decoder. - Purushotham Murugappa; Amer Baghdadi; Michel Jézéquel (DATE, 2013)

Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohana; Youssef Atat (DATE, 2013)

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. - Carlo Condo; Amer Baghdadi; Guido Masera (DSD, 2013)

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Michael Hübner 001; Jean-Philippe Diguet (DSD, 2013)

Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohanna; Youssef Atat (ICCIT, 2013)

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Jean-Philippe Diguet; Jean-Noel Bazin; Michael Hübner 001 (ISCAS, 2013)

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Jean-Philippe Diguet; Jean-Noel Bazin; Michael Hübner 001 (ISVLSI, 2013)

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. - Vianney Lapotre; Michael Hübner 001; Guy Gogniat; Purushotham Murugappa; Amer Baghdadi; Jean-Philippe Diguet (ReCoSoC, 2013)

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. - Purushotham Murugappa; Vianney Lapotre; Amer Baghdadi; Michel Jézéquel (RSP, 2013)

Energy-efficient FPGA implementation for binomial option pricing using OpenCL. - Valentin Mena Morales; Pierre-Henri Horrein; Amer Baghdadi; Erik Hochapfel; Sandrine Vaton (DATE, 2014)

UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN. - Houcine Chougrani; Jean Schwoerer; Pierre-Henri Horrein; Amer Baghdadi; Francois Dehmas (ICECS, 2014)

Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohanna; Youssef Atat (RSP, 2014)

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. - Carlo Condo; Amer Baghdadi; Guido Masera (IET Commun., 2014)

Caasper: providing accessible FPGA-acceleration over the network. - Valentin Mena Morales; Yahia Brakni; Pierre-Henri Horrein; Amer Baghdadi (RSP, 2015)

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. - Carlo Condo; Amer Baghdadi; Guido Masera (Circuits Syst. Signal Process., 2015)

NISC-Based Soft-Input-Soft-Output Demapper. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohanna; Youssef Atat (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. - Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Michael Hübner 001; Jean-Philippe Diguet (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Towards memristor-based reconfigurable FFT architecture. - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah (ICM, 2017)

Flexible hardware platform for demonstrating new 5G waveform candidates. - Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (ICM, 2017)

NoC-MRAM architecture for memory-based computing: Database-search case study. - Mostafa Rizk; Jean-Philippe Diguet; Naoya Onizawa; Amer Baghdadi; Martha Johanna Sepúlveda; Y. Akgul; Vincent Gripon; Takahiro Hanyu (NEWCAS, 2017)

Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter. - Said Medjkouh; Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (SiPS, 2017)

High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards. - Atif Raza Jafri; Amer Baghdadi; Muhammad Waqas 003; Muhammad Najam-ul-Islam (IEEE Access, 2017)

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding. - Vianney Lapotre; Guy Gogniat; Amer Baghdadi; Jean-Philippe Diguet (EURASIP J. Adv. Signal Process., 2017)

Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohanna; Youssef Atat (EURASIP J. Embed. Syst., 2017)

Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD. - Atif Raza Jafri; Amer Baghdadi; Muhammad Najam-ul-Islam; Michel Jézéquel (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Block FBMC Receiver Designed for Short Filters. - Jérémy Nadal; François Leduc-Primeau; Charbel Abdel Nour; Amer Baghdadi (ICC, 2018)

NISC Design Experience of Flexible Architectures for Digital Communication Applications. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Ali Chamas Al Ghouwayel (ICCA, 2018)

Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper. - Muhammad Waqas 003; Atif Raza Jafri; Amer Baghdadi; Muhammad Najam-ul-Islam (RSP, 2018)

Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. - Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (IEEE Access, 2018)

Networked Power-Gated MRAMs for Memory-Based Computing. - Jean-Philippe Diguet; Naoya Onizawa; Mostafa Rizk; Martha Johanna Sepúlveda; Amer Baghdadi; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation. - Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (IEEE Trans. Veh. Technol., 2018)

MRL Crossbar-Based Full Adder Design. - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah (ICECS, 2019)

Crossbar Memory Architecture Performing Memristor Overwrite Logic. - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah (ICECS, 2019)

Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel (J. Circuits Syst. Comput., 2019)

Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN. - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah (ISCAS, 2020)

FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. - Jérémy Nadal; Amer Baghdadi (RSP, 2020)

Memristive Computational Memory Using Memristor Overwrite Logic (MOL). - Khaled Alhaj Ali; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet; Jalal Jomaah; Naoya Onizawa; Takahiro Hanyu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Overlap-Save FBMC Receivers. - Jérémy Nadal; François Leduc-Primeau; Charbel Abdel Nour; Amer Baghdadi (IEEE Trans. Wirel. Commun., 2020)

Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm. - Hugo Le Blevec; Rami Klaimi; Stefan Weithoffer; Charbel Abdel Nour; Amer Baghdadi (ISTC, 2021)

No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Yasser Mohanna; Youssef Atat (Des. Autom. Embed. Syst., 2021)

NISC-Based MIMO MMSE Detector. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel; Youssef Atat; Yasser Mohanna (J. Circuits Syst. Comput., 2021)

Hardware Implementation of Overlap-Save-Based Fading Channel Emulator. - Muhammad Najam-ul-Islam; Muhammad Nauman; Atif Raza Jafri; Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA. - Jérémy Nadal; Amer Baghdadi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Low Latency Architecture Design for Decoding 5G NR Polar Codes. - Oualid Mouhoubi; Charbel Abdel Nour; Amer Baghdadi (DASIP, 2022)

Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices. - Mostafa Rizk; Dominique Heller; R. Douguet; Amer Baghdadi; Jean-Philippe Diguet (ICECS 2022, 2022)

On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes. - Oualid Mouhoubi; Charbel Abdel Nour; Amer Baghdadi (ISIVC, 2022)

Marine Objects Detection Using Deep Learning on Embedded Edge Devices. - Dominique Heller; Mostafa Rizk; R. Douguet; Amer Baghdadi; Jean-Philippe Diguet (RSP, 2022)

Enhancing embedded AI-based object detection using multi-view approach. - Z. Ning; Mostafa Rizk; Amer Baghdadi; Jean-Philippe Diguet (RSP, 2022)

Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning. - Mostafa Rizk; Fatima Slim; Amer Baghdadi; Jean-Philippe Diguet (SYSINT, 2022)

Overlap-Save FBMC receivers for massive MIMO systems under channel impairments. - Fatima Hamdar; Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (VTC Spring, 2022)

Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes. - Oualid Mouhoubi; Charbel Abdel Nour; Amer Baghdadi (IEEE Access, 2022)

A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping. - Mostafa Rizk; Amer Baghdadi; Michel Jézéquel (J. Circuits Syst. Comput., 2022)

MOL-Based In-Memory Computing of Binary Neural Networks. - Khaled Alhaj Ali; Amer Baghdadi; Elsa Dupraz; Mathieu Léonardon; Mostafa Rizk; Jean-Philippe Diguet (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Novel transmission technique based on intentional overlapping for spectral efficiency enhancement in multicarrier systems. - Fatima Hamdar; Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (PIMRC, 2023)

Overlap-Save FBMC Receivers for Massive MIMO Systems. - Fatima Hamdar; Jérémy Nadal; Charbel Abdel Nour; Amer Baghdadi (IEEE Trans. Wirel. Commun., 2024)