A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors. - Amin Aghighi; Abdul Hafiz Alameh; Mohammad Taherzadeh-Sani; Frederic Nabki (ICECS, 2016)

Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. - Jacob Atkinson; Amin Aghighi; Stuart Anderson; Anthony Bailey; Mitchell Crane; Armin Tajalli (MWSCAS, 2019)

CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. - Amin Aghighi; Jacob Atkinson; Nickolas Bybee; Stuart Anderson; Mitchell Crane; Anthony Bailey; Reuben Morell; Ahmed Hassanin; Armin Tajalli (NEWCAS, 2019)

Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. - Amin Aghighi; Behrouz Farhang-Boroujeny; Armin Tajalli (VLSI-SOC, 2020)

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. - Amin Aghighi; Behrouz Farhang-Boroujeny; Armin Tajalli (VLSI-SoC (Selected Papers), 2020)

An ULP Self-Supplied Brain Interface Circuit. - Amin Aghighi; Massood Tabib-Azar; Armin Tajalli (VLSI-SOC, 2020)

A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. - Amin Aghighi; Armin Tajalli; Mohammad Taherzadeh-Sani (VLSI-SOC, 2020)

A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive. - Mostafa Essawy; Kareem Rashed; Amin Aghighi; Arun Natarajan 001 (IEEE J. Solid State Circuits, 2024)