Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure. - Amin Chegeni; Khayrollah Hadidi; Abdollah Khoei (ICECS, 2007)

Input dependent clock jitter in high speed and high resolution ADCs. - Amin Chegeni; Reza Shayanfar; Khayrollah Hadidi; Abdollah Khoei (ISCAS, 2012)

CMOS implementation of a fast 4-2 compressor for parallel accumulations. - Amir Fathi; Sarkis Azizian; Khayrollah Hadidi; Abdollah Khoei; Amin Chegeni (ISCAS, 2012)

A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs. - Amin Chegeni; Khayrollah Hadidi; Abdollah Khoei (IEEE Trans. Circuits Syst. II Express Briefs, 2018)