Multi-tone signaling for high-speed backplane electrical links. - Amir Amirkhany; Vladimir Stojanovic; Mark A. Horowitz (GLOBECOM, 2004)

Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication. - Vladimir Stojanovic; Amir Amirkhany; Mark A. Horowitz (ICC, 2004)

Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links. - Amir Amirkhany; Ali-Azam Abbasfar; Vladimir Stojanovic; Mark A. Horowitz (GLOBECOM, 2006)

Time-Variant Characterization and Compensation of Wideband Circuits. - Amir Amirkhany; Ali-Azam Abbasfar; Jafar Savoj; Mark A. Horowitz (CICC, 2007)

A new technique for characterization of digital-to-analog converters in high-speed systems. - Jafar Savoj; Ali-Azam Abbasfar; Amir Amirkhany; Bruno W. Garlepp; Mark A. Horowitz (DATE, 2007)

Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links. - Amir Amirkhany; Ali-Azam Abbasfar; Vladimir Stojanovic; Mark A. Horowitz (ICC, 2007)

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. - Amir Amirkhany; Aliazam Abbasfar; Jafar Savoj; Metha Jeeradit; Bruno W. Garlepp; Ravi T. Kollipara; Vladimir Stojanovic; Mark Horowitz (IEEE J. Solid State Circuits, 2008)

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. - Jafar Savoj; Aliazam Abbasfar; Amir Amirkhany; Metha Jeeradit; Bruno W. Garlepp (IEEE J. Solid State Circuits, 2008)

A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. - Mahmoud Reza Ahmadi; Amir Amirkhany; Ramesh Harjani (CICC, 2009)

A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links. - Mahmoud Reza Ahmadi; Amir Amirkhany; Ramesh Harjani (IEEE J. Solid State Circuits, 2010)

A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces. - Farshid Aryanfar; Amir Amirkhany (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

On overcoming the limitations of single-ended signaling for graphics memory interfaces. - Amir Amirkhany; Wendemagegnehu T. Beyene; Chris J. Madden; Aliazam Abbasfar; Dave Secker; Dan Oh; Mohammad Hekmat; Ralf Schmitt; Chuck Yuan (A-SSCC, 2011)

Power-efficient I/O design considerations for high-bandwidth applications. - John C. Eble; Scott Best; Brian S. Leibowitz; Lei Luo 006; Robert Palmer; John M. Wilson 002; Jared Zerbe; Amir Amirkhany; Nhat Nguyen (CICC, 2011)

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. - Navin K. Mishra; Manish Jain; Phuong Le; Sanku Mukherjee; Arul Sendhil; Amir Amirkhany (CICC, 2011)

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (ISSCC, 2012)

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. - Kambiz Kaviani; Amir Amirkhany; Charlie Huang; Phuong Le; Chris J. Madden; Keisuke Saito; Koji Sano; Vinod Murugan; Wendemagegnehu T. Beyene; Ken Chang; Chuck Yuan (ISSCC, 2012)

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (IEEE J. Solid State Circuits, 2012)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)

A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS. - Kwangmo Jung; Amir Amirkhany; Kambiz Kaviani (ISSCC, 2013)

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver. - Kambiz Kaviani; Amir Amirkhany; Charlie Huang; Phuong Le; Wendemagegnehu T. Beyene; Chris J. Madden; Keisuke Saito; Koji Sano; Vinod Inipodu Murugan; Kun-Yung Ken Chang; Xingchao Chuck Yuan (IEEE J. Solid State Circuits, 2013)

23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. - Mohammad Hekmat; Sanquan Song; Nancy Jaffari; Sabarish Sankaranarayanan; Chaofeng Huang; Minghui Han; Gaurav Malhotra; Jalil Kamali; Amir Amirkhany; Wei Xiong (ISSCC, 2016)

A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. - Anup P. Jose; Valentin Abramzon; Mohamed Elzeftawi; Michael Wang; Kyunglok Kim; Younghoon Song; Shiva Moballegh; Jalil Kamali; Amir Amirkhany (CICC, 2019)

Baud rate pattern-adaptable dual loop clock recovery for high speed serial links. - Gaurav Malhotra; Jalil Kamali; Amir Amirkhany (ACSCC, 2021)

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. - Mike Shuo-Wei Chen; Wei-Zen Chen; Amir Amirkhany (ISSCC, 2021)

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). - Amir Amirkhany; Tanay Karnik; Shidhartha Das; Jun Deguchi; Yasuhiko Taito (IEEE J. Solid State Circuits, 2022)

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. - Tianyu Wang 006; Da Wei; Ranick Ng; Gaurav Malhotra; Anup P. Jose; Amir Amirkhany; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2022)