MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2015)

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (DFT, 2016)

Addressing transient routing errors in fault-tolerant Networks-on-Chips. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (ETS, 2016)

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (ASP-DAC, 2017)

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs. - Amir Charif; Nacer-Eddine Zergainoh; Alexandre Coelho; Michael Nicolaidis (ETS, 2017)

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (LATS, 2017)

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations. - Juan A. Fraire; Pablo G. Madoery; Scott C. Burleigh; Marius Feldmann; Jorge M. Finochietto; Amir Charif; Nacer-Eddine Zergainoh; Raoul Velazco (J. Comput. Networks Commun., 2017)

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (VLSI Design, 2017)

A soft-error resilient route computation unit for 3D Networks-on-Chips. - Alexandre Coelho; Amir Charif; Nacer-Eddine Zergainoh; Juan A. Fraire; Raoul Velazco (DATE, 2018)

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip. - Alexandre Coelho; Amir Charif; Nacer-Eddine Zergainoh; Raoul Velazco (DFT, 2018)

On route table computation strategies in Delay-Tolerant Satellite Networks. - Juan A. Fraire; Pablo G. Madoery; Amir Charif; Jorge M. Finochietto (Ad Hoc Networks, 2018)

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. - Amir Charif; Alexandre Coelho; Masoumeh Ebrahimi; Nader Bagherzadeh; Nacer-Eddine Zergainoh (IEEE Trans. Computers, 2018)

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design. - Arief Wicaksana; Amir Charif; Caaliph Andriamisaina; Nicolas Ventroux (DASIP, 2019)

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration. - Amir Charif; Gabriel Busnot; Rania H. Mameesh; Tanguy Sassolas; Nicolas Ventroux (RAPIDO, 2019)

Fast Virtual Prototyping of Cyber-Physical Systems using SystemC and FMI: ADAS Use Case. - Salah Eddine Saidi; Amir Charif; Tanguy Sassolas; Pierre-Guillaume Le Guay; Henrique Vicente Souza; Nicolas Ventroux (RSP, 2019)

A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (IEEE Trans. Emerg. Top. Comput., 2020)

Decoupling processor and memory hierarchy simulators for efficient design space exploration. - Fatma Jebali; Oumaima Matoussi; Arief Wicaksana; Amir Charif; Lilia Zaourar (DroneSE/RAPIDO@HiPEAC, 2022)